Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency

• SHIOYA Ryota

  Graduate School of Engineering, Nagoya University

• ANDO Hideki

  Graduate School of Engineering, Nagoya University

Abstract

Out-of-order superscalar processors rename register numbers to remove false dependencies between instructions. A renaming logic for register renaming is a high-cost module in a superscalar processor, and it consumes considerable energy. A renamed trace cache (RTC) was proposed for reducing the energy consumption of a renaming logic. An RTC caches and reuses renamed operands, and thus, register renaming can be omitted on RTC hits. However, conventional RTCs suffer from several performance, energy consumption, and hardware overhead problems. We propose a semi-global renamed trace cache (SGRTC) that caches only renamed operands that are short distance from producers outside traces, and solves the problems of conventional RTCs. Evaluation results show that SGRTC achieves 64% lower energy consumption for renaming with a 0.2% performance overhead as compared to a conventional processor.

Journal

• IEICE Transactions on Information and Systems

  IEICE Transactions on Information and Systems E99.D (3), 630-640, 2016

  The Institute of Electronics, Information and Communication Engineers

Keywords

• superscalar processor
• register renaming
• trace cache
• energy efficiency

Details

• CRID: 1390282679354157440
• NII Article ID: 130005131824
• DOI: 10.1587/transinf.2015edp7270
• ISSN: 17451361
• ISSN: 09168532
• Web Site: https://www.jstage.jst.go.jp/article/transinf/E99.D/3/E99.D_2015EDP7270/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed