Timing Monitoring Paths Selection for Wide Voltage IC

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著者

    • Shan Weiwei
    • National ASIC system and research engineering center, Southeast University
    • Dai Wentao
    • National ASIC system and research engineering center, Southeast University
    • Cao Peng
    • National ASIC system and research engineering center, Southeast University

抄録

Wide voltage range circuit has got widespread attention where in-situ timing monitoring based adaptive voltage scaling (AVS) becomes necessary to reduce the design margin. However, the severe PVT variations across near-threshold to super-threshold cause too many critical paths to be monitored. Here activation oriented monitoring paths selection method is proposed to reduce the monitored paths for wide voltage IC. The minimum delay value of the longest activated path is found by dynamic timing analysis and set as the selection threshold. Those paths longer than this threshold by STA analysis are selected to be monitored. Applied on a 40nm AVS System-on-Chip, it reduces the monitoring paths to only 22% of all critical paths with remarkable power gains under 0.6V-1.1V.

収録刊行物

  • IEICE Electronics Express

    IEICE Electronics Express advpub(0), 2016

    一般社団法人 電子情報通信学会

各種コード

  • NII論文ID(NAID)
    130005142174
  • 本文言語コード
    EN
  • ISSN
    1349-2543
  • データ提供元
    J-STAGE 
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