A 12 to 24 GHz high efficiency fully integrated 0.18 µm CMOS power amplifier
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- Mosalam Hamed
- Electronics and Communications Engineering Dept., Egypt-Japan University of Science and Technology
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- Allam Ahmed
- Electronics and Communications Engineering Dept., Egypt-Japan University of Science and Technology
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- Jia Hongting
- E-JUST Center, Kyushu University
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- Abdelrahman Adel
- Electronics and Communications Engineering Dept., Egypt-Japan University of Science and Technology
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- Kaho Takana
- E-JUST Center, Kyushu University
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- Pokharel Ramesh
- E-JUST Center, Kyushu University
抄録
<p>This letter presents a high efficiency, and small group delay variations 12–24 GHz fully-integrated CMOS power amplifier (PA) for quasi-millimeter wave applications. Maximizing the power added efficiency (PAE), and minimizing the group delay variations in a wideband frequency range are achieved by optimizing the on-chip input, output, and inter-stage matching circuits. In addition, stagger tuning is employed for realizing excellent gain flatness. A two-stage CMOS PA using the proposed methodology is designed and fabricated in 0.18 µm CMOS technology and tested. A measured power gain (|S21|) of 10.5 ± 0.7 dB and a measured small group delay variation of ±20 ps over the frequency range of interest are achieved. The PA shows a maximum measured PAE to be 26 % with DC power consumption of 50 mW.</p>
収録刊行物
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- IEICE Electronics Express
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IEICE Electronics Express 13 (14), 20160551-20160551, 2016
一般社団法人 電子情報通信学会
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詳細情報 詳細情報について
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- CRID
- 1390282680195971968
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- NII論文ID
- 130005166220
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- ISSN
- 13492543
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
- KAKEN
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- 抄録ライセンスフラグ
- 使用不可