A 12 to 24 GHz high efficiency fully integrated 0.18 µm CMOS power amplifier

• Mosalam Hamed

  Electronics and Communications Engineering Dept., Egypt-Japan University of Science and Technology

• Allam Ahmed

  Electronics and Communications Engineering Dept., Egypt-Japan University of Science and Technology

• Jia Hongting

  E-JUST Center, Kyushu University

• Abdelrahman Adel

  Electronics and Communications Engineering Dept., Egypt-Japan University of Science and Technology

• Kaho Takana

  E-JUST Center, Kyushu University

• Pokharel Ramesh

  E-JUST Center, Kyushu University

Abstract

This letter presents a high efficiency, and small group delay variations 12–24 GHz fully-integrated CMOS power amplifier (PA) for quasi-millimeter wave applications. Maximizing the power added efficiency (PAE), and minimizing the group delay variations in a wideband frequency range are achieved by optimizing the on-chip input, output, and inter-stage matching circuits. In addition, stagger tuning is employed for realizing excellent gain flatness. A two-stage CMOS PA using the proposed methodology is designed and fabricated in 0.18 µm CMOS technology and tested. A measured power gain (|S₂₁|) of 10.5 ± 0.7 dB and a measured small group delay variation of ±20 ps over the frequency range of interest are achieved. The PA shows a maximum measured PAE to be 26 % with DC power consumption of 50 mW.

Journal

• IEICE Electronics Express

  IEICE Electronics Express 13 (14), 20160551-20160551, 2016

  The Institute of Electronics, Information and Communication Engineers

Keywords

• power-added efficiency (PAE)
• power amplifier (PA)
• quasi-millimeter wave band
• CMOS

Details

• CRID: 1390282680195971968
• NII Article ID: 130005166220
• DOI: 10.1587/elex.13.20160551
• ISSN: 13492543
• Web Site: https://www.jstage.jst.go.jp/article/elex/13/14/13_13.20160551/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed