Analytical Stability Modeling for CMOS Latches in Low Voltage Operation

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  • KAMAKARI Tatsuya
    Department of Communications and Computer Engineering, Kyoto University
  • SHIOMI Jun
    Department of Communications and Computer Engineering, Kyoto University
  • ISHIHARA Tohru
    Department of Communications and Computer Engineering, Kyoto University
  • ONODERA Hidetoshi
    Department of Communications and Computer Engineering, Kyoto University CREST, JST

Abstract

<p>In synchronous LSI circuits, memory subsystems such as Flip-Flops and SRAMs are essential components and latches are the base elements of the common memory logics. In this paper, a stability analysis method for latches operating in a low voltage region is proposed. The butterfly curve of latches is a key for analyzing a retention failure of latches. This paper discusses a modeling method for retention stability and derives an analytical stability model for latches. The minimum supply voltage where the latches can operate with a certain yield can be accurately derived by a simple calculation using the proposed model. Monte-Carlo simulation targeting 65nm and 28nm process technology models demonstrates the accuracy and the validity of the proposed method. Measurement results obtained by a test chip fabricated in a 65nm process technology also demonstrate the validity. Based on the model, this paper shows some strategies for variation tolerant design of latches.</p>

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