GPU-Accelerated Bulk Execution of Multiple-Length Multiplication with Warp-Synchronous Programming Technique

• HONDA Takumi

  Department of Information Engineering, Hiroshima University

• ITO Yasuaki

  Department of Information Engineering, Hiroshima University

• NAKANO Koji

  Department of Information Engineering, Hiroshima University

抄録

In this paper, we present a GPU implementation of bulk multiple-length multiplications. The idea of our GPU implementation is to adopt a warp-synchronous programming technique. We assign each multiple-length multiplication to one warp that consists of 32 threads. In parallel processing using multiple threads, usually, it is costly to synchronize execution of threads and communicate within threads. In warp-synchronous programming technique, however, execution of threads in a warp can be synchronized instruction by instruction without any barrier synchronous operations. Also, inter-thread communication can be performed by warp shuffle functions without accessing shared memory. The experimental results show that our GPU implementation on NVIDIA GeForce GTX 980 attains a speed-up factor of 52 for 1024-bit multiple-length multiplication over the sequential CPU implementation. Moreover, we use this 1024-bit multiple-length multiplication for larger size of bits as a sub-routine. The GPU implementation attains a speed-up factor of 21 for 65536-bit multiple-length multiplication.

収録刊行物

• IEICE Transactions on Information and Systems

  IEICE Transactions on Information and Systems E99.D (12), 3004-3012, 2016

  一般社団法人 電子情報通信学会

キーワード

• multiple-length multiplication
• GPU
• GPGPU
• parallel processing
• warp-synchronous

詳細情報

• CRID: 1390282679355964288
• NII論文ID: 130005170988
• DOI: 10.1587/transinf.2016pap0027
• ISSN: 17451361
• ISSN: 09168532
• Web Site: https://www.jstage.jst.go.jp/article/transinf/E99.D/12/E99.D_2016PAP0027/_pdf
• 本文言語コード: en
• データソース種別:
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