An FPGA Implementation for a Flexible-Length-Arithmetic Processor Employing the FDFM Processor Core Approach

• KAWAMOTO Tatsuya

  Department of Information Engineering, Hiroshima University

• ZHOU Xin

  Department of Information Engineering, Hiroshima University

• BORDIM Jacir L.

  Department of Computer Science, University of Brasilia

• ITO Yasuaki

  Department of Information Engineering, Hiroshima University

• NAKANO Koji

  Department of Information Engineering, Hiroshima University

抄録

Algorithms requiring fast manipulation of multiple-length numbers are usually implemented in hardware. However, hardware implementation, using HDL (Hardware Description Language) for instance, is a laborious task and the quality of the solution relies heavily on the designer expertise. The main contribution of this work is to present a flexible-length-arithmetic processor based on FDFM (Few DSP slices and Few Memory blocks) approach that supports arithmetic operations on multiple-length numbers using FPGAs (Field Programmable Gate Array). The proposed processor has been implement on the Xilinx Virtex-6 FPGA. Arithmetic instructions of the proposed processor architecture include addition, subtraction, and multiplication of integer numbers exceeding 64-bits. To reduce the burden of implementing algorithm directly on the FPGA, applications requiring multiple-length arithmetic operations are written in a C-like language and translated into a machine program. The machine program is then transferred and executed on the proposed architecture. A 2048-bit RSA encryption/decryption implementation has been used to assess the goodness of the proposed approach. Experimental results shows that the computing time, using the proposed architecture, of a 2048-bit RSA encryption takes only 2.2 times longer than a direct FPGA implementation. Furthermore, by employing multiple FDFM cores for the same task, the computing time reduces considerably.

収録刊行物

• IEICE Transactions on Information and Systems

  IEICE Transactions on Information and Systems E99.D (12), 2901-2910, 2016

  一般社団法人 電子情報通信学会

キーワード

• multiple-length-numbers
• multiple-length-arithmetic
• FPGA
• RSA
• montgomery modular multiplication

詳細情報

• CRID: 1390001204379254272
• NII論文ID: 130005170989
• DOI: 10.1587/transinf.2016pap0029
• ISSN: 17451361
• ISSN: 09168532
• Web Site: https://www.jstage.jst.go.jp/article/transinf/E99.D/12/E99.D_2016PAP0029/_pdf
• 本文言語コード: en
• データソース種別:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• 抄録ライセンスフラグ: 使用不可