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- AKIMA Hisanao
- Research Institute of Electrical Communication, Tohoku University
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- KATAYAMA Yasuhiro
- Toshiba Corporation Semiconductor & Storage Products Company
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- SAKURABA Masao
- Research Institute of Electrical Communication, Tohoku University
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- NAKAJIMA Koji
- Research Institute of Electrical Communication, Tohoku University
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- MADRENAS Jordi
- Department of Electronic Engineering, Universitat Politècnica de Catalunya
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- SATO Shigeo
- Research Institute of Electrical Communication, Tohoku University
抄録
<p>Majority logic is quite important for various applications such as fault tolerant systems, threshold logic, spectrum spread coding, and artificial neural networks. The circuit implementation of majority logic is difficult when the number of inputs becomes large because the number of transistors becomes huge and serious delay would occur. In this paper, we propose a new majority circuit with large fan-in. The circuit is composed of ordinary CMOS transistors and the total number of transistors is approximately only 4N, where N is the total number of inputs. We confirmed a correct operation by using HSPICE simulation. The yield of the proposed circuit was evaluated with respect to N under the variations of device parameters by using Monte Carlo simulation.</p>
収録刊行物
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- IEICE Transactions on Electronics
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IEICE Transactions on Electronics E99.C (9), 1056-1064, 2016
一般社団法人 電子情報通信学会
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詳細情報 詳細情報について
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- CRID
- 1390282679356806528
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- NII論文ID
- 130005262050
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- ISSN
- 17451353
- 09168524
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
- KAKEN
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- 抄録ライセンスフラグ
- 使用不可