Stochastic TDC Architecture with Self-Calibration and its RTL Verification

• Li Congbing

  Division of Electronics and Informatics, Gunma University

• Wang Junshan

  Division of Electronics and Informatics, Gunma University

• Kobayashi Haruo

  Division of Electronics and Informatics, Gunma University

• Shiota Ryoji

  Socionext Inc.

Abstract

A time-to-digital converter (TDC) based on stochastic process and statistics theory is presented. This architecture utilizes the stochastic variation in CMOS process positively for fine time resolution. It needs a large number of flip-flops for statistics but advanced fine CMOS technology can realize it. The self-calibration technique using the histogram method is applied to compensate the nonlinearity due to the circuit characteristics variation as well as timing skew by layout and routing. The proposed TDC can be implemented with full digital circuit, which is suitable as nano-CMOS mixed-signal circuit. Register-Transfer-Level (RTL) simulation is conducted to validate the operation principle. RTL verification results indicate that the proposed stochastic architecture with self-calibration feature can realize a linear TDC with sub-picosecond time resolution.

Journal

• IEEJ Transactions on Electronics, Information and Systems

  IEEJ Transactions on Electronics, Information and Systems 137 (2), 335-341, 2017

  The Institute of Electrical Engineers of Japan

Keywords

• Timing Measurement
• Stochastic
• Time to Digital Converter
• Self-calibration
• FPGA

Details

• CRID: 1390282679583782016
• NII Article ID: 130005308472
• NII Book ID: AN10065950
• DOI: 10.1541/ieejeiss.137.335
• ISSN: 13488155
• ISSN: 03854221
• NDL BIB ID: 027968329
• Web Site: http://id.ndl.go.jp/bib/027968329
• Web Site: https://ndlsearch.ndl.go.jp/books/R000000004-I027968329
• Web Site: https://www.jstage.jst.go.jp/article/ieejeiss/137/2/137_335/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • NDL
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed