The Performance Evaluation of a 3D Torus Network Using Partial Link-Sharing Method in NoC Router Buffer

• FUKASE Naohisa

  Graduate School of Technology, Shonan Institute of Technology

• MIURA Yasuyuki

  Graduate School of Technology, Shonan Institute of Technology

• WATANABE Shigeyoshi

  Graduate School of Technology, Shonan Institute of Technology

• HAFIZUR RAHMAN M.M.

  Dept. of Computer Science, KICT, International Islamic University

抄録

The high performance network-on-chip (NoC) router using minimal hardware resources to minimize the layout area is very essential for NoC design. In this paper, we have proposed a memory sharing method of a wormhole routed NoC architecture to alleviate the area overhead of a NoC router. In the proposed method, a memory is shared by multiple physical links by using a multi-port memory. In this paper, we have proposed a partial link-sharing method and evaluated the communication performance using the proposed method. It is revealed that the resulted communication performance by the proposed methods is higher than that of the conventional method, and the progress ratio of the 3D-torus network is higher than that of 2D-torus network. It is shown that the improvement of communication performance using partial link sharing method is achieved with slightly increase of hardware cost.

収録刊行物

• IEICE Transactions on Information and Systems

  IEICE Transactions on Information and Systems E100.D (10), 2478-2492, 2017

  一般社団法人 電子情報通信学会

キーワード

• interconnection network
• network-on-chip (NoC)
• router
• multi-port memory

詳細情報

• CRID: 1390001204379487488
• NII論文ID: 130006110291
• DOI: 10.1587/transinf.2017edp7031
• ISSN: 17451361
• ISSN: 09168532
• Web Site: https://www.jstage.jst.go.jp/article/transinf/E100.D/10/E100.D_2017EDP7031/_pdf
• 本文言語コード: en
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