Hardware Oriented Low-Complexity Intra Coding Algorithm for SHVC

DOI Web Site 17 References
  • KATAYAMA Takafumi
    Department of Electrical and Electronics Engineering, The University of Tokushima
  • SONG Tian
    Department of Electrical and Electronics Engineering, The University of Tokushima
  • SHI Wen
    Department of Electrical and Electronics Engineering, The University of Tokushima
  • FUJITA Gen
    Department of Engineering Informatics, Osaka Electro-Communication University
  • JIANG Xiantao
    Department of Electrical and Electronics Engineering, The University of Tokushima
  • SHIMAMOTO Takashi
    Department of Electrical and Electronics Engineering, The University of Tokushima

Abstract

<p>Scalable high efficiency video coding (SHVC) can provide variable video quality according to terminal devices. However, the computational complexity of SHVC is increased by introducing new techniques based on high efficiency video coding (HEVC). In this paper, a hardware oriented low complexity algorithm is proposed. The hardware oriented proposals have two key points. Firstly, the coding unit depth is determined by analyzing the boundary correlation between coding units before encoding process starts. Secondly, the redundant calculation of R-D optimization is reduced by adaptively using the information of the neighboring coding units and the co-located units in the base layer. The simulation results show that the proposed algorithm can achieve over 62% computation complexity reduction compared to the original SHM11.0. Compared with other related work, over 11% time saving have been achieved without PSNR loss. Furthermore, the proposed algorithm is hardware friendly which can be implemented in a small area.</p>

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