A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT
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- YOSHIMURA Masayoshi
- Faculty of Computer Science and Engineering, Kyoto Sangyo University
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- TAKAHASHI Yoshiyasu
- Graduate School of Industrial Technology, Nihon University
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- YAMAZAKI Hiroshi
- College of Industrial Technology, Nihon University
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- HOSOKAWA Toshinori
- College of Industrial Technology, Nihon University
Abstract
<p>High power dissipation can occur by high launch-induced switching activity when the response to a test pattern is captured by flip-flops (FFs) in at-speed scan testing, resulting in excessive IR drop. IR drop may cause significant capture-induced yield loss in the deep submicron era. It is known that test modification methods using X-identification and X-filling are effective to reduce power dissipation in the capture cycle. Conventional low power dissipation oriented X-filling methods consecutively select FFs and assign values to decrease the number of transitions on the FFs. In this paper, we propose a novel low power dissipation oriented X-filling method using SAT Solvers that conducts simultaneous X-filling for some FFs. We also proposed a selection order of FFs based on a correlation coefficient between transitions of FFs and power dissipation. Experimental results show that the proposed method was effective for ISCAS'89 and ITC'99 benchmark circuits compared with justification-probability-based fill.</p>
Journal
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- IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100.A (12), 2824-2833, 2017
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1390282681291651584
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- NII Article ID
- 130006236532
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- ISSN
- 17451337
- 09168508
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- Text Lang
- en
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- Data Source
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- JaLC
- Crossref
- CiNii Articles
- KAKEN
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- Abstract License Flag
- Disallowed