A Proposal for Downconverting A-to-D Converter Based on Even-Harmonic Mixer and ΔΣ-TDC

• Takahashi Takuto

  Department of Electrical and Electronic Engineering, Kitami Institute of Technology

• Sugimoto Toshiki

  Department of Electrical and Electronic Engineering, Kitami Institute of Technology

• Tanimoto Hiroshi

  Department of Electrical and Electronic Engineering, Kitami Institute of Technology

• Yoshizawa Shingo

  Department of Electrical and Electronic Engineering, Kitami Institute of Technology

Abstract

A novel architecture of downconverting A-to-D Converter is proposed, which is based on even-harmonic mixer and ΔΣ Time-to-Digital Converter. Analog circuits are minimized by the proposed architecture. As a design study, a test chip of 200 MHz RF signal to baseband downconverter is designed and fabricated. The design uses a standard 0.18 µm CMOS technology, and the simulation results verify the operation of the proposed architecture. Measurement result is presented and it verified the functionality of the fabricated test chip.

Journal

• IEEJ Transactions on Electronics, Information and Systems

  IEEJ Transactions on Electronics, Information and Systems 138 (1), 50-56, 2018

  The Institute of Electrical Engineers of Japan

Keywords

• even-harmonic mixer
• delta-sigma-TDC
• A-to-D Converter
• downconverter
• direct conversion
• Time-to-Digital Converter

Details

• CRID: 1390001204611428480
• NII Article ID: 130006301502
• NII Book ID: AN10065950
• DOI: 10.1541/ieejeiss.138.50
• ISSN: 13488155
• ISSN: 03854221
• NDL BIB ID: 028782082
• Web Site: http://id.ndl.go.jp/bib/028782082
• Web Site: https://ndlsearch.ndl.go.jp/books/R000000004-I028782082
• Web Site: https://www.jstage.jst.go.jp/article/ieejeiss/138/1/138_50/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • NDL
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed