A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers

• YAMAMOTO Takahiro

  Ritsumeikan University

• TANIGUCHI Ittetsu

  Ritsumeikan University

• TOMIYAMA Hiroyuki

  Ritsumeikan University

• YAMASHITA Shigeru

  Ritsumeikan University

• HARA-AZUMI Yuko

  Tokyo Institute of Technology

Abstract

Approximate computing is considered as a promising approach to design of power- or area-efficient digital circuits. This paper proposes a systematic methodology for design and worst-case accuracy analysis of approximate array multipliers. Our methodology systematically designs a series of approximate array multipliers with different area, delay, power and accuracy characteristics so that an LSI designer can select the one which best fits to the requirements of her/his applications. Our experiments explore the trade-offs among area, delay, power and accuracy of the approximate multipliers.

Journal

• IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100.A (7), 1496-1499, 2017

  The Institute of Electronics, Information and Communication Engineers

Keywords

• approximate computing
• array multipliers
• SMT solver

Details

• CRID: 1390282681287057664
• NII Article ID: 130007311789
• DOI: 10.1587/transfun.e100.a.1496
• ISSN: 17451337
• ISSN: 09168508
• Web Site: https://www.jstage.jst.go.jp/article/transfun/E100.A/7/E100.A_1496/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed