A Low-Power and GHz-Band <i>LC</i>-DCO Directly Drives 10mm On-Chip Clock Distribution Line in 0.18µm CMOS

• ICHIHASHI Masahiro

  Graduate School of Information Science and Electrical Engineering, Kyushu University

• KANAYA Haruichi

  Graduate School of Information Science and Electrical Engineering, Kyushu University

抄録

High-speed clock distribution design is becoming increasingly difficult and challenging task due to the huge power consumption and jitter caused by large capacitive loading and multiple repeater stages. This paper proposes a novel low-power, GHz-band bufferless LC-DCO which directly drives 10 mm on-chip clock distribution line for high-speed serial links. The shared LC-tank structure between DCO frequency tuning capacitor and clock distribution line mitigate the frequency sensitivity and makes an energy-efficient, area-saving, high-speed operation possible. The test-chip is implemented under TSMC 0.18µm, 1-poly, 6-metal CMOS technology and the core area of proposed LC-DCO is only 270×280µm². The full-chip post layout simulation results show 2.54GHz oscillation frequency, 2.2mA current consumption and phase noise of -123dBc/Hz at 1MHz offset.

収録刊行物

• IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E101.A (11), 1907-1914, 2018-11-01

  一般社団法人 電子情報通信学会

キーワード

• LC-DCO
• bufferless
• clock distribution
• serial links

詳細情報

• CRID: 1390564238038880128
• NII論文ID: 130007502856
• DOI: 10.1587/transfun.e101.a.1907
• ISSN: 17451337
• ISSN: 09168508
• Web Site: https://www.jstage.jst.go.jp/article/transfun/E101.A/11/E101.A_1907/_pdf
• 本文言語コード: en
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