Area Reduction Technique for Digital Circuit Part in Non-Binary Analog-to-Digital Converter

• Shindo Yuji

  Tokyo City University

• Seto Kenshu

  Tokyo City University

• San Hao

  Tokyo City University

Bibliographic Information

Other Title

• 非2進展開に基づくAD変換器のデジタル回路部面積削減手法
• ヒ2シン テンカイ ニ モトズク AD ヘンカンキ ノ デジタル カイロブ メンセキ サクゲン シュホウ

Abstract

We propose an area reduction method of digital circuit part in β-expansion-based analog-to-digital converter (ADC). The digital parts of conventional β-expansion based ADCs use lookup table (LUT) to estimate effective β values, and to convert non-binary digital output from analog part to binary code. Unfortunately, increasing the conversion resolution (bit number) of the ADCs increases the chip area of the LUT. In this work, we estimate the effective β values by Newton's method and directly convert non-binary numbers to binary numbers without LUTs. As a result, when the conversion resolution of the ADCs is increased, the proposed method reduces the increase of the digital part area compared to the conventional LUT-based method.

Journal

• IEEJ Transactions on Electronics, Information and Systems

  IEEJ Transactions on Electronics, Information and Systems 139 (1), 76-82, 2019-01-01

  The Institute of Electrical Engineers of Japan

Keywords

• AD Converter
• high-level synthesis

Details

• CRID: 1390845713037101312
• NII Article ID: 130007542148
• NII Book ID: AN10065950
• DOI: 10.1541/ieejeiss.139.76
• ISSN: 13488155
• ISSN: 03854221
• NDL BIB ID: 029440184
• Web Site: https://ndlsearch.ndl.go.jp/books/R000000004-I029440184
• Web Site: https://www.jstage.jst.go.jp/article/ieejeiss/139/1/139_76/_pdf
• Text Lang: ja
• Data Source:
  • JaLC
  • NDL
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed