Current Pass Optimized Symmetric Pass Gate Adiabatic Logic for Cryptographic Circuits

• Koyasu Hiroki

  Graduate School of Natural Science and Technology, Gifu University

• Takahashi Yasuhiro

  Graduate School of Natural Science and Technology, Gifu University

抄録

We propose a new adiabatic logic for cryptographic circuits, called as the Current Pass Optimized Symmetric Pass Gate Adiabatic Logic (CPO-SPGAL). The proposed circuit realizes a flat current waveform by considering the current path. The simulation results demonstrate that the proposed circuit can reduce the current fluctuation by approximately 84% and reduce the energy consumption fluctuation by approximately 79% as compared to the existing SPGAL circuits. This shows that it is more resistant to differential power analysis attacks than conventional circuits.

収録刊行物

• IPSJ Transactions on System LSI Design Methodology

  IPSJ Transactions on System LSI Design Methodology 12 (0), 50-52, 2019

  一般社団法人 情報処理学会

キーワード

• adiabatic logic
• dual rail logic
• secure
• current trace

詳細情報

• CRID: 1390282763100846848
• NII論文ID: 130007603009
• DOI: 10.2197/ipsjtsldm.12.50
• ISSN: 18826687
• Web Site: https://www.jstage.jst.go.jp/article/ipsjtsldm/12/0/12_50/_pdf
• 本文言語コード: en
• データソース種別:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• 抄録ライセンスフラグ: 使用不可