A 24-bit sigma-delta ADC with configurable chopping scheme

DOI Web Site 被引用文献2件 参考文献19件
  • Li Li
    State Key Laboratory of ASIC and System, Fudan University
  • Cheng Xu
    State Key Laboratory of ASIC and System, Fudan University
  • Zhang Zhang
    School of Electronic Science and Applied Physics, Hefei University of Technology
  • Zeng Jianmin
    School of Electronic Science and Applied Physics, Hefei University of Technology
  • Zeng Xiaoyang
    State Key Laboratory of ASIC and System, Fudan University

抄録

<p>This paper presents a low-power high-precision sigma-delta analog-to-digital converter (ADC) mainly used for DC measurement, especially in applications with high input impedance. A configurable chopping scheme is proposed to reduce the input-dependent residual offset caused by the clock feed-through. Furthermore, it also improves noise performance in the first integrator. The 1.17 mm2 chip is fabricated in a standard 65 nm CMOS process. Measurement results show that the ADC achieves 20-bit resolution, 10 ppm INL and a 0.6 µV offset, while consuming 860 µW from 3.3 V supply.</p>

収録刊行物

  • IEICE Electronics Express

    IEICE Electronics Express 16 (10), 20190176-20190176, 2019

    一般社団法人 電子情報通信学会

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