A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS

DOI Web Site 被引用文献2件 参考文献21件
  • Chen Xubin
    School of Aeronautics and Astronautics, Zhejiang University
  • Li Xuan
    China Academy of Space Technology
  • Shen Yupeng
    School of Aeronautics and Astronautics, Zhejiang University
  • Liu Jiarui
    School of Aeronautics and Astronautics, Zhejiang University
  • Chen Hua
    School of Aeronautics and Astronautics, Zhejiang University

抄録

<p>In this paper, a 14 bit 500 MS/s SHA-less pipelined Analog-to-Digital Converter (ADC) realized in 40 nm CMOS technology is presented. A 2.5 V powered buffer that exhibits a comprehensive bootstrap architecture is proposed to achieve the trade-off between linearity and power consumption. Besides, the high-voltage-thin-oxide-device design is incorporated to further improve the linearity. In the meantime, an improved supply voltage domain arrangement is proposed to achieve a single power design and improve structural power efficiency. The measured Signal-to-Noise-and-Distortion-Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) are 71 dB and 79 dBc at 120.2 MHz input signal under 500 MS/s. The ADC occupies an active area of 0.4 mm2 and consumes a total power of 300 mW.</p>

収録刊行物

  • IEICE Electronics Express

    IEICE Electronics Express 16 (11), 20190197-20190197, 2019

    一般社団法人 電子情報通信学会

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