Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity

• TSUCHIYA Akira

  The University of Shiga Prefecture

• HIRATSUKA Akitaka

  Kyoto University

• INOUE Toshiyuki

  The University of Shiga Prefecture

• KISHINE Keiji

  The University of Shiga Prefecture

• ONODERA Hidetoshi

  Kyoto University

Abstract

This paper discusses the impact of stacking on-chip inductor on power/ground network. Stacking inductor on other circuit components can reduce the circuit area drastically, however, the impact on signal and power integrity is not clear. We investigate the impact by a field-solver, a circuit simulator and real chip measurement. We evaluate three types of power/ground network and various multi-layered inductors. Experimental results show that dense power/ground structures reduce noise although the coupling capacitance becomes larger than that of sparse structures. Measurement in a 65-nm CMOS shows a woven structure makes the noise voltage half compared to a sparse structure.

Journal

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E102.C (7), 573-579, 2019-07-01

  The Institute of Electronics, Information and Communication Engineers

Keywords

• power integrity
• signal integrity
• multi-layered inductor

Details

• CRID: 1390001288150524288
• NII Article ID: 130007671361
• DOI: 10.1587/transele.2018ctp0007
• ISSN: 17451353
• ISSN: 09168524
• Web Site: https://www.jstage.jst.go.jp/article/transele/E102.C/7/E102.C_2018CTP0007/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed