16 Gビット/秒シリアル信号伝送シミュレーションに関するFPGA搭載ボードを用いた検証  [in Japanese] Verification of the Simulation Result Concerning 16-Gbit/s Serial Signal Transmission by Using the Printed Circuit Board with FPGA  [in Japanese]

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Author(s)

    • 本木 浩之 Motoki Hiroyuki
    • RITAエレクトロニクス株式会社開発・ソリューション本部 Research, Development & Solution Division, RITA Electronics, Ltd.
    • 田中 顕裕 Tanaka Akihiro
    • RITAエレクトロニクス株式会社開発・ソリューション本部 Research, Development & Solution Division, RITA Electronics, Ltd.

Abstract

<p>To acquire knowledge about the accuracy and effectiveness of a simulation for high-speed signal communication, we prepared several boards, each with an FPGA which corresponds to 16 Gbit/s serial signal transmitting and receiving. We then measured their eye patterns and BERs, and compared the actual measurement results to the simulated ones. Regarding the eye patterns observed in a 50 Ω terminated environment with an oscilloscope, the simulations agree very well with the experiments. This shows that simulation is effective for selecting the material of the printed wiring board before the pattern design and the emphasis condition of the transmitting signal. On the other hand, for the FPGA reception BER, the simulation results tend to be better than the actual measurements, so it is necessary to consider this in simulation operation.</p>

Journal

  • Journal of The Japan Institute of Electronics Packaging

    Journal of The Japan Institute of Electronics Packaging 22(4), 301-306, 2019

    The Japan Institute of Electronics Packaging

Codes

  • NII Article ID (NAID)
    130007672029
  • Text Lang
    JPN
  • ISSN
    1343-9677
  • Data Source
    J-STAGE 
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