Design and theoretical analysis of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges

• Niitsu Kiichi

  Graduate School of Engineering, Nagoya University

• Kobayashi Osamu

  STARC

• Yamaguchi Takahiro J.

  Graduate School of Engineering, Gunma University

• Kobayashi Haruo

  STARC

抄録

This study demonstrates the design and theoretical analysis of a clock jitter reduction circuit that exploits the phase blending technique between the uncorrelated clock edges that are self-delayed by multiples of the clock cycle, nT. By blending uncorrelated clock edges, the output clock edges approach the ideal timing and, thus, timing jitter can be reduced by a factor of √2 per stage. There are three technical challenges to realize this: 1) generating uncorrelated clock edges, 2) phase averaging with small time offset from the ideal center position, and 3) minimizing the error in nT-delay being deviated from ideal nT. The proposed circuit overcomes each of these by exploiting an nT-delay, gated phase blending, and self-calibrated nT-delay elements, respectively. Measurement results with a 180-nm CMOS prototype chip demonstrated an approximately four-fold reduction in timing jitter from 30.2 ps to 8.8 ps in 500-MHz clock by cascading the proposed circuit with four-stages. Theoretical analysis for evaluating the limit of jitter reduction is also presented.

収録刊行物

• IEICE Electronics Express

  IEICE Electronics Express 16 (13), 20190218-20190218, 2019

  一般社団法人 電子情報通信学会

キーワード

• jitter
• jitter reduction
• phase blending
• self-delayed
• PLL

詳細情報

• CRID: 1390282763129289472
• NII論文ID: 130007677138
• DOI: 10.1587/elex.16.20190218
• ISSN: 13492543
• Web Site: https://www.jstage.jst.go.jp/article/elex/16/13/16_16.20190218/_pdf
• 本文言語コード: en
• データソース種別:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• 抄録ライセンスフラグ: 使用不可