A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines

• OKU Daisuke

  Department of Computer Science and Communications Engineering, Waseda University

• TERADA Kotaro

  Department of Computer Science and Communications Engineering, Waseda University

• HAYASHI Masato

  Hitachi, Ltd.

• YAMAOKA Masanao

  Hitachi, Ltd.

• TANAKA Shu

  Green Computing Systems Research Organization, Waseda University Precursory Research for Embryonic Science and Technology, Japan Science and Technology Agency

• TOGAWA Nozomu

  Department of Computer Science and Communications Engineering, Waseda University

Abstract

Combinatorial optimization problems with a large solution space are difficult to solve just using von Neumann computers. Ising machines or annealing machines have been developed to tackle these problems as a promising Non-von Neumann computer. In order to use these annealing machines, every combinatorial optimization problem is mapped onto the physical Ising model, which consists of spins, interactions between them, and their external magnetic fields. Then the annealing machines operate so as to search the ground state of the physical Ising model, which corresponds to the optimal solution of the original combinatorial optimization problem. A combinatorial optimization problem can be firstly described by an ideal fully-connected Ising model but it is very hard to embed it onto the physical Ising model topology of a particular annealing machine, which causes one of the largest issues in annealing machines. In this paper, we propose a fully-connected Ising model embedding method targeting for CMOS annealing machine. The key idea is that the proposed method replicates every logical spin in a fully-connected Ising model and embeds each logical spin onto the physical spins with the same chain length. Experimental results through an actual combinatorial problem show that the proposed method obtains spin embeddings superior to the conventional de facto standard method, in terms of the embedding time and the probability of obtaining a feasible solution.

Journal

• IEICE Transactions on Information and Systems

  IEICE Transactions on Information and Systems E102.D (9), 1696-1706, 2019-09-01

  The Institute of Electronics, Information and Communication Engineers

Keywords

• CMOS annealing
• Ising model
• Ising computing
• graph embedding
• combinatorial optimization

Details

• CRID: 1390001277344872320
• NII Article ID: 130007699802
• DOI: 10.1587/transinf.2018edp7411
• ISSN: 17451361
• ISSN: 09168532
• Web Site: https://www.jstage.jst.go.jp/article/transinf/E102.D/9/E102.D_2018EDP7411/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed