Weighted Bit-Flipping Decoding of LDPC Codes with LLR Adjustment for MLC Flash Memories

• ZHANG Xuan

  School of Computer Science and Technology, Xidian University

• JIAO Xiaopeng

  School of Computer Science and Technology, Xidian University

• HE Yu-Cheng

  Xiamen Key Laboratory of Mobile Multimedia Communications, Huaqiao University State Key Laboratory of Integrated Services Networks, Xidian University

• MU Jianjun

  School of Computer Science and Technology, Xidian University

抄録

Low-density parity-check (LDPC) codes can be used to improve the storage reliability of multi-level cell (MLC) flash memories because of their strong error-correcting capability. In order to improve the weighted bit-flipping (WBF) decoding of LDPC codes in MLC flash memories with cell-to-cell interference (CCI), we propose two strategies of normalizing weights and adjusting log-likelihood ratio (LLR) values. Simulation results show that the WBF decoding under the proposed strategies is much advantageous in both error and convergence performances over existing WBF decoding algorithms. Based on complexity analysis, the strategies provide the WBF decoding with a good tradeoff between performance and complexity.

収録刊行物

• IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E102.A (11), 1571-1574, 2019-11-01

  一般社団法人 電子情報通信学会

キーワード

• multi-level cell (MLC)
• cell-to-cell interference
• LDPC codes
• weighted bit-flipping decoding

詳細情報

• CRID: 1390845702310416000
• NII論文ID: 130007740132
• DOI: 10.1587/transfun.e102.a.1571
• ISSN: 17451337
• ISSN: 09168508
• Web Site: https://www.jstage.jst.go.jp/article/transfun/E102.A/11/E102.A_1571/_pdf
• 本文言語コード: en
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