Optimized Charge Pump and Nonlinear Phase Frequency Detector for a Ka-Band Phase-Locked Loop in 90-nm CMOS Process
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- TANG Lu
- Institute of RF- & OE-ICs, Southeast University Quantum Information Research Center, Southeast University
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- WANG Zhigong
- Institute of RF- & OE-ICs, Southeast University
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- FAN Tiantian
- Institute of RF- & OE-ICs, Southeast University
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- LIU Faen
- Institute of RF- & OE-ICs, Southeast University
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- ZHANG Changchun
- College of Electronic and Optical Engineering & College of Microelectronics, Nanjing University of Posts and Telecommunications
抄録
<p>In this paper, an improved charge pump (CP) and a modified nonlinear phase frequency detector (PFD) are designed and fabricated in a 90-nm CMOS process. The CP is optimized with a combination of circuit techniques such as pedestal error cancel scheme to eliminate the charge injection and the other non-ideal characteristics. The nonlinear PFD is based on a modified circuit topology to enhance the acquisition capability of the PLL. The optimized CP and nonlinear PFD are integrated into a Ka-band PLL. The measured output current mismatch ratio of the improved CP is less than 1% when the output voltage Vout fluctuates between 0.2 to 1.1V from a 1.2V power supply. The measured phase error detection range of the modified nonlinear PFD is between -2π and 2π. Owing to the modified CP and PFD, the measured reference spur of the Ka-band PLL frequency synthesizer containing the optimized CP and PFD is only -56.409dBc at 30-GHz at the locked state.</p>
収録刊行物
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- IEICE Transactions on Electronics
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IEICE Transactions on Electronics E102.C (11), 825-832, 2019-11-01
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詳細情報 詳細情報について
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- CRID
- 1390282752357396992
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- NII論文ID
- 130007740357
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- ISSN
- 17451353
- 09168524
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可