An Accuracy-Configurable Adder for Low-Power Applications

• YANG Tongxin

  Graduate School of Information and Control Systems, Fukuoka University

• SATO Toshinori

  Department of Electronics Engineering and Computer Science, Fukuoka University

• UKEZONO Tomoaki

  Department of Electronics Engineering and Computer Science, Fukuoka University

抄録

Addition is a key fundamental function for many error-tolerant applications. Approximate addition is considered to be an efficient technique for trading off energy against performance and accuracy. This paper proposes a carry-maskable adder whose accuracy can be configured at runtime. The proposed scheme can dynamically select the length of the carry propagation to satisfy the quality requirements flexibly. Compared with a conventional ripple carry adder and a conventional carry look-ahead adder, the proposed 16-bit adder reduced the power consumption by 54.1% and 57.5%, respectively, and the critical path delay by 72.5% and 54.2%, respectively. In addition, results from an image processing application indicate that the quality of processed images can be controlled by the proposed adder. Good scalability of the proposed adder is demonstrated from the evaluation results using a 32-bit length.

収録刊行物

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E103.C (3), 68-76, 2020-03-01

  一般社団法人 電子情報通信学会

キーワード

• approximate computing
• accuracy-configurable adder
• carry-maskable adder
• low-power adder

詳細情報

• CRID: 1390846609809044224
• NII論文ID: 130007804173
• DOI: 10.1587/transele.2019lhp0002
• ISSN: 17451353
• ISSN: 09168524
• Web Site: https://www.jstage.jst.go.jp/article/transele/E103.C/3/E103.C_2019LHP0002/_pdf
• 本文言語コード: en
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