A charge recycling stacked I/O in standard CMOS technology for wide TSV data bus
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- Yoshikawa Takefumi
- Dept. of Electrical and Computer Engineering, Toyama Prefectural University
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- Iwata Tatsuya
- Dept. of Electrical and Computer Engineering, Toyama Prefectural University
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- Shibazaki Junji
- Dept. of Electrical and Computer Engineering, Toyama Prefectural University
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- Muroga Sho
- Graduate School of Engineering Science, Akita University
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- Ikeda Hiroaki
- Graduate School of Science, Technology and Innovation, Kobe University
Abstract
<p>This paper describes theoretical approach and proposed scheme of wide data bus architecture using charge-recycling and stacked I/O for signal transmission via TSV (Through Silicon Via). This data bus is assumed for vertical stacked chips of 3D integration. This theoretical approach is based on probability calculation for data stream on pure random pattern. Through the calculation, power reduction ratio to normal data bus (non-charge recycling) is clarified in given conditions for power estimation in early design stage. The proposed scheme for data and clock transmission adopts Local Voltage Stabilizer (LVS) and compact level shifter for capacitor area and clock power reduction. Simulation results show that the proposed 2 story data bus architectures of 64bits (32×2) and 128bits (64×2) achieve competitive power efficiency (0.160pJ/bit) with smaller size (44% to prior work) and normal operation voltage (1V). These achievements are in dense TSVs (40μm pitch), standard 65nm process technology and PRBS9 data stream.</p>
Journal
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- IEICE Electronics Express
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IEICE Electronics Express 17 (10), 20200112-20200112, 2020-05-25
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1390285300159256576
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- NII Article ID
- 130007846254
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- ISSN
- 13492543
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- Text Lang
- en
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- Data Source
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- JaLC
- Crossref
- CiNii Articles
- KAKEN
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- Abstract License Flag
- Disallowed