RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining
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- MIYAZAKI Hiromu
- School of Computing, Tokyo Institute of Technology
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- KANAMORI Takuto
- School of Computing, Tokyo Institute of Technology
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- ISLAM Md Ashraful
- School of Computing, Tokyo Institute of Technology
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- KISE Kenji
- School of Computing, Tokyo Institute of Technology
Abstract
<p>RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. Three effective methods are applied to the processor to improve the operating frequency. These methods are instruction fetch unit optimization, ALU optimization, and data memory optimization. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.</p>
Journal
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- IEICE Transactions on Information and Systems
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IEICE Transactions on Information and Systems E103.D (12), 2494-2503, 2020-12-01
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1391693801397236992
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- NII Article ID
- 130007948564
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- ISSN
- 17451361
- 09168532
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- Text Lang
- en
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- Data Source
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- JaLC
- Crossref
- CiNii Articles
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- Abstract License Flag
- Disallowed