FPGA Implementation of a Binarized Dual Stream Convolutional Neural Network for Service Robots
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- Yoshimoto Yuma
- Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology Japan Society for the Promotion of Science
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- Tamukoh Hakaru
- Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology Research Center for Neuromorphic AI Hardware, Kyushu Institute of Technology
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<p>In this study, with the aim of installing an object recognition algorithm on the hardware device of a service robot, we propose a Binarized Dual Stream VGG-16 (BDS-VGG16) network model to realize high-speed computations and low power consumption. The BDS-VGG16 model has improved in terms of the object recognition accuracy by using not only RGB images but also depth images. It achieved a 99.3% accuracy in tests using an RGB-D Object Dataset. We have also confirmed that the proposed model can be installed in a field-programmable gate array (FPGA). We have further installed BDS-VGG16 Tiny, a small BDS-VGG16 model in XCZU9EG, a system on a chip with a CPU and a middle-scale FPGA on a single chip that can be installed in robots. We have also integrated the BDS-VGG16 Tiny with a robot operating system. As a result, the BDS-VGG16 Tiny installed in the XCZU9EG FPGA realizes approximately 1.9-times more computations than the one installed in the graphics processing unit (GPU) with a power efficiency approximately 8-times higher than that installed in the GPU.</p>
収録刊行物
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- Journal of Robotics and Mechatronics
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Journal of Robotics and Mechatronics 33 (2), 386-399, 2021-04-20
富士技術出版株式会社
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詳細情報 詳細情報について
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- CRID
- 1390287750912817920
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- NII論文ID
- 130008027729
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- NII書誌ID
- AA10809998
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- ISSN
- 18838049
- 09153942
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- HANDLE
- 10228/00008265
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- NDL書誌ID
- 031402263
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- en
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