The Fractional-N All Digital Frequency Locked Loop with Robustness for PVT Variation and Its Application for the Microcontroller Unit
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- MIYAUCHI Ryoichi
- Tokyo University of Science
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- YOSHIDA Akio
- ROHM Co., Ltd.
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- NAKANO Shuya
- University of Miyazaki
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- TAMURA Hiroki
- University of Miyazaki
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- TANNO Koichi
- University of Miyazaki
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- FUKUCHI Yutaka
- Tokyo University of Science
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- KAWAMURA Yukio
- LAPIS Semiconductor Co., Ltd.
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- KODAMA Yuki
- LAPIS Semiconductor Co., Ltd.
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- SEKIYA Yuichi
- LAPIS Semiconductor Co., Ltd.
Abstract
<p>This paper describes the Fractional-N All Digital Frequency Locked Loop (ADFLL) with Robustness for PVT variation and its application for the microcontroller unit. The conventional FLL is difficult to achieve the required specification by using the fine CMOS process. Especially, the conventional FLL has some problems such as unexpected operation and long lock time that are caused by PVT variation. To overcome these problems, we propose a new ADFLL which uses dynamic selecting digital filter coefficients. The proposed ADFLL was evaluatied through the HSPICE simulation and fabricating chips using a 0.13 µm CMOS process. From these results, we observed the proposed ADFLL has robustness for PVT variation by using dynamic selecting digital filter coefficient, and the lock time is improved up to 57%, clock jitter is 0.85 nsec.</p>
Journal
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- IEICE Transactions on Information and Systems
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IEICE Transactions on Information and Systems E104.D (8), 1146-1153, 2021-08-01
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1390851862123168000
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- NII Article ID
- 130008070396
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- ISSN
- 17451361
- 09168532
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- Text Lang
- en
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- Data Source
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- JaLC
- Crossref
- CiNii Articles
- KAKEN
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- Abstract License Flag
- Disallowed