Fabrication Process for Superconducting Digital Circuits

• HIDAKA Mutsuo

  AIST

• NAGASAWA Shuichi

  AIST

抄録

This review provides a current overview of the fabrication processes for superconducting digital circuits at CRAVITY (clean room for analog and digital superconductivity) at the National Institute of Advanced Industrial Science and Technology (AIST), Japan. CRAVITY routinely fabricates superconducting digital circuits using three types of fabrication processes and supplies several thousand chips to its collaborators each year. Researchers at CRAVITY have focused on improving the controllability and uniformity of device parameters and the reliability, which means reducing defects. These three aspects are important for the correct operation of large-scale digital circuits. The current technologies used at CRAVITY permit ±10% controllability over the critical current density (J_c) of Josephson junctions (JJs) with respect to the design values, while the critical current (I_c) uniformity is within 1σ=2% for JJs with areas exceeding 1.0 µm² and the defect density is on the order of one defect for every 100,000 JJs.

収録刊行物

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E104.C (9), 405-410, 2021-09-01

  一般社団法人 電子情報通信学会

キーワード

• superconducting integrated circuits
• Josephson junction
• fabrication process
• controllability
• uniformity
• defect density

詳細情報

• CRID: 1390007757214558848
• NII論文ID: 130008082178
• DOI: 10.1587/transele.2020sui0002
• ISSN: 17451353
• ISSN: 09168524
• Web Site: https://www.jstage.jst.go.jp/article/transele/E104.C/9/E104.C_2020SUI0002/_pdf
• 本文言語コード: en
• データソース種別:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
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