Planarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device Evaluation
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- NAGASAWA Shuichi
- AIST
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- TANAKA Masamitsu
- Nagoya University
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- TAKEUCHI Naoki
- Yokohama National University
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- YAMANASHI Yuki
- Yokohama National University
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- MIYAJIMA Shigeyuki
- NICT
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- CHINA Fumihiro
- NICT
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- YAMAE Taiki
- Yokohama National University
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- YAMAZAKI Koki
- The University of Electro-Communications
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- SOMEI Yuta
- The University of Electro-Communications
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- SEGA Naonori
- The University of Electro-Communications
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- MIZUGAKI Yoshinao
- The University of Electro-Communications
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- MYOREN Hiroaki
- Saitama University
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- TERAI Hirotaka
- NICT
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- HIDAKA Mutsuo
- AIST
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- YOSHIKAWA Nobuyuki
- Yokohama National University
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- FUJIMAKI Akira
- Nagoya University
抄録
<p>We developed a Nb 4-layer process for fabricating superconducting integrated circuits that involves using caldera planarization to increase the flexibility and reliability of the fabrication process. We call this process the planarized high-speed standard process (PHSTP). Planarization enables us to flexibly adjust most of the Nb and SiO2 film thicknesses; we can select reduced film thicknesses to obtain larger mutual coupling depending on the application. It also reduces the risk of intra-layer shorts due to etching residues at the step-edge regions. We describe the detailed process flows of the planarization for the Josephson junction layer and the evaluation of devices fabricated with PHSTP. The results indicated no short defects or degradation in junction characteristics and good agreement between designed and measured inductances and resistances. We also developed single-flux-quantum (SFQ) and adiabatic quantum-flux-parametron (AQFP) logic cell libraries and tested circuits fabricated with PHSTP. We found that the designed circuits operated correctly. The SFQ shift-registers fabricated using PHSTP showed a high yield. Numerical simulation results indicate that the AQFP gates with increased mutual coupling by the planarized layer structure increase the maximum interconnect length between gates.</p>
収録刊行物
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- IEICE Transactions on Electronics
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IEICE Transactions on Electronics E104.C (9), 435-445, 2021-09-01
一般社団法人 電子情報通信学会
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詳細情報 詳細情報について
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- CRID
- 1390570707166953728
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- NII論文ID
- 130008082182
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- ISSN
- 17451353
- 09168524
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
- KAKEN
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