Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison

• MATSUDA Yasutaka

  Department of Information and Communication Engineering, Nagoya University

• SHIOYA Ryota

  Department of Creative Informatics, Graduate School of Information Science and Technology, The University of Tokyo

• ANDO Hideki

  Department of Information and Communication Engineering, Nagoya University

抄録

The high energy consumption of current processors causes several problems, including a limited clock frequency, short battery lifetime, and reduced device reliability. It is therefore important to reduce the energy consumption of the processor. Among resources in a processor, the issue queue (IQ) is a large consumer of energy, much of which is consumed by the wakeup logic. Within the wakeup logic, the tag comparison that checks source operand readiness consumes a significant amount of energy. This paper proposes an energy reduction scheme for tag comparison, called double-stage tag comparison. This scheme first compares the lower bits of the tag and then, only if these match, compares the higher bits. Because the energy consumption of tag comparison is roughly proportional to the total number of bits compared, energy is saved by reducing this number. However, this sequential comparison increases the delay of the IQ, thereby increasing the clock cycle time. Although this can be avoided by allocating an extra cycle to the issue operation, this in turn degrades the IPC. To avoid IPC degradation, we reconfigure a small number of entries in the IQ, where several oldest instructions that are likely to have an adverse effect on performance reside, to a single stage for tag comparison. Our evaluation results for SPEC2017 benchmark programs show that the double-stage tag comparison achieves on average a 21% reduction in the energy consumed by the wakeup logic (15% when including the overhead) with only 3.0% performance degradation.

収録刊行物

• IEICE Transactions on Information and Systems

  IEICE Transactions on Information and Systems E105.D (2), 320-332, 2022-02-01

  一般社団法人 電子情報通信学会

キーワード

• microprocessor
• superscalar processor
• instruction-level parallelism
• issue queue
• power consumption

詳細情報

• CRID: 1390572404751425280
• NII論文ID: 130008149967
• DOI: 10.1587/transinf.2021edp7174
• ISSN: 17451361
• ISSN: 09168532
• Web Site: https://www.jstage.jst.go.jp/article/transinf/E105.D/2/E105.D_2021EDP7174/_pdf
• 本文言語コード: en
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