Effects of high-temperature diluted-H<sub>2</sub> annealing on effective mobility of 4H-SiC MOSFETs with thermally-grown SiO<sub>2</sub>

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<jats:title>Abstract</jats:title> <jats:p>The impact of post-oxidation annealing (POA) in diluted-H<jats:sub>2</jats:sub> ambient on a 4H-SiC/SiO<jats:sub>2</jats:sub> interface was investigated with a cold wall furnace. Effective mobility (μ<jats:sub>eff</jats:sub>) was extracted from lateral metal–oxide–semiconductor field-effect transistors (MOSFETs) by applying the split capacitance–voltage (<jats:italic>C</jats:italic>–<jats:italic>V</jats:italic>) technique to the determination of charge density and a calibration technique using two MOSFETs with different gate lengths to minimize the contribution of parasitic components. POA at 1150 °C in diluted-H<jats:sub>2</jats:sub> ambient resulted in an enhancement of μ<jats:sub>eff</jats:sub> compared with that for POA in N<jats:sub>2</jats:sub> ambient. It was indicated that the effects of POA in diluted H<jats:sub>2</jats:sub> should be attributed to the reduction in the density of near interface traps, which disturb the electron transportation in the inversion channel, from the measurement temperature dependence of μ<jats:sub>eff</jats:sub> as well as from the <jats:italic>C</jats:italic>–<jats:italic>V</jats:italic> curves of MOS capacitors fabricated on n-type SiC.</jats:p>

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