Scaling limit for InGaAs/GaAsSb heterojunction double-gate tunnel FETs from the viewpoint of direct band-to-band tunneling from source to drain induced off-characteristics deterioration
抄録
<jats:title>Abstract</jats:title> <jats:p>In this paper, we propose a method to classify the tunneling currents using simulations. The main objective is to investigate the effects of the direct source-to-drain tunneling, which is undesirable, in the case of devices with extremely short channels. We performed the classification of tunneling currents in InGaAs/GaAsSb heterojunction double-gate tunnel FETs based on this method, and we found that the direct-tunneling component increased dramatically in short-channel cases. The channel length must be 20 nm or longer, in case of InGaAs/GaAsSb heterojunction double-gate tunnel FETs, to limit the off-current within 10 pA/µm, which is required as per the ITRS LP.</jats:p>
収録刊行物
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- Japanese Journal of Applied Physics
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Japanese Journal of Applied Physics 55 (7), 070303-, 2016-06-21
IOP Publishing
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詳細情報 詳細情報について
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- CRID
- 1360003449890620672
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- NII論文ID
- 210000146742
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- ISSN
- 13474065
- 00214922
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