Image processing using CMOS variable threshold logic on bit-mapping CAD system ビットマップCAD上におけるCMOS可変しきい値論理を用いた画像処理に関する研究

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Author

    • 高窪, 統 タカクボ, ハジメ

Bibliographic Information

Title

Image processing using CMOS variable threshold logic on bit-mapping CAD system

Other Title

ビットマップCAD上におけるCMOS可変しきい値論理を用いた画像処理に関する研究

Author

高窪, 統

Author(Another name)

タカクボ, ハジメ

University

上智大学

Types of degree

工学博士

Grant ID

甲第118号

Degree year

1992-03-31

Note and Description

博士論文

Table of Contents

  1. Contents / p1 (0004.jp2)
  2. I. Introduction / p1 (0005.jp2)
  3. 1. Background / p1 (0005.jp2)
  4. 2. Purpose and Contents of Thesis / p4 (0007.jp2)
  5. References / p6 (0008.jp2)
  6. II. A Bitmap Memory Bank of Region access / p10 (0010.jp2)
  7. Abstract / p10 (0010.jp2)
  8. 1. Introduction / p11 (0010.jp2)
  9. 2. System Construction Employing Bitmap Memory Bank / p12 (0011.jp2)
  10. 3. Hardware Configuration / p15 (0012.jp2)
  11. 4. Software Structure / p17 (0013.jp2)
  12. 5. Breadboard implementation / p18 (0014.jp2)
  13. 6. Twin chips implementation / p20 (0015.jp2)
  14. 7. Evaluation of Bitmap Memory Bank / p21 (0016.jp2)
  15. 8. Conclusions / p23 (0015.jp2)
  16. References / p25 (0017.jp2)
  17. Figures / p26 (0018.jp2)
  18. III. Combination Analog and Digital Circuits using CMOS Variable Threshold Logic / p39 (0024.jp2)
  19. Abstract / p39 (0024.jp2)
  20. 1. Introduction / p40 (0025.jp2)
  21. 2. Design Principle of the Simple Chip / p41 (0025.jp2)
  22. 3. Advanced Approach / p45 (0027.jp2)
  23. 4. Discussion / p48 (0029.jp2)
  24. 5. Conclusions / p50 (0030.jp2)
  25. References / p51 (0030.jp2)
  26. Figures / p52 (0031.jp2)
  27. IV. A Gray Image Binarization using CMOS Variable Threshold Logic / p61 (0035.jp2)
  28. Abstract / p61 (0035.jp2)
  29. 1. Introduction / p62 (0036.jp2)
  30. 2. System Configuration / p63 (0036.jp2)
  31. 3. Principle of the Adaptive Threshold Binarization / p64 (0037.jp2)
  32. 4. Hardware Implementation / p67 (0038.jp2)
  33. 5. Results and Discussion / p70 (0040.jp2)
  34. 6. Conclusion / p71 (0040.jp2)
  35. References / p72 (0041.jp2)
  36. Figures / p74 (0042.jp2)
  37. V. An Image Tracing Approach Using CMOS Variable Threshold Logic / p83 (0046.jp2)
  38. Abstract / p83 (0046.jp2)
  39. 1. Introduction / p84 (0047.jp2)
  40. 2. System configuration / p85 (0047.jp2)
  41. 3. Principle of tracing approach / p88 (0049.jp2)
  42. 4. Hardware Implementation / p92 (0051.jp2)
  43. 5. Results and Discussion / p94 (0052.jp2)
  44. 6. Application Example / p95 (0052.jp2)
  45. 7. Conclusions / p96 (0053.jp2)
  46. References / p97 (0053.jp2)
  47. Figures / p99 (0054.jp2)
  48. VI. Concluding Remarks / p109 (0059.jp2)
  49. Acknowledgments / p112 (0061.jp2)
  50. List of Publications / p113 (0061.jp2)
5access

Codes

  • NII Article ID (NAID)
    500000083612
  • NII Author ID (NRID)
    • 8000000083822
  • DOI(NDL)
  • NDLBibID
    • 000000247926
  • Source
    • NDL ONLINE
    • NDL Digital Collections

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