A study of hazard detection and fault analysis for VLSI circuits VLSIのハザード検出及び故障解析に関する研究

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Author

    • 康, 敏燮 カン, ミンソップ

Bibliographic Information

Title

A study of hazard detection and fault analysis for VLSI circuits

Other Title

VLSIのハザード検出及び故障解析に関する研究

Author

康, 敏燮

Author(Another name)

カン, ミンソップ

University

大阪大学

Types of degree

工学博士

Grant ID

甲第4570号

Degree year

1992-03-25

Note and Description

博士論文

Table of Contents

  1. ABSTRACT / p1 (0003.jp2)
  2. TABLE OF CONTENTS / p4 (0006.jp2)
  3. ABSTRACT / p1 (0003.jp2)
  4. TABLE OF CONTENTS / p4 (0006.jp2)
  5. 1.Introduction / p1 (0009.jp2)
  6. 1.1 Backgrounds / p1 (0009.jp2)
  7. 1.2 Outline of the Dissertation / p4 (0012.jp2)
  8. 2.Digital Logic Simulation / p7 (0015.jp2)
  9. 2.1 Introduction / p7 (0015.jp2)
  10. 2.2 Logic Simulation / p7 (0015.jp2)
  11. 2.3 Fault Analysis / p13 (0021.jp2)
  12. 3.Hazard Detection by 5-Valued Logic Simulation / p17 (0025.jp2)
  13. 3.1 Introduction / p17 (0025.jp2)
  14. 3.2 Problem of Min/Max Delay Model / p18 (0026.jp2)
  15. 3.3 Transition Rise/Fall Delay Model / p20 (0028.jp2)
  16. 3.4 Simulation Algorithm / p23 (0031.jp2)
  17. 3.5 Hazard Analysis / p25 (0033.jp2)
  18. 3.6 Event Cancellation / p31 (0039.jp2)
  19. 3.7 Experimental Results / p31 (0039.jp2)
  20. 3.8 Conclusion / p37 (0045.jp2)
  21. 4.Fault Modeling for nMOS/CMOS Devices / p39 (0047.jp2)
  22. 4.1 Introduction / p39 (0047.jp2)
  23. 4.2 Conventional Fault Model / p41 (0049.jp2)
  24. 4.3 Simulation Model Based on Switch Box / p43 (0051.jp2)
  25. 4.4 Simulation Model Based on Collapsed Fault Sets / p56 (0064.jp2)
  26. 4.5 Fault Collapsing / p60 (0068.jp2)
  27. 4.6 Experimental Results / p62 (0070.jp2)
  28. 4.7 Conclusion / p63 (0071.jp2)
  29. 5.High Speed Fault Simulation / p64 (0072.jp2)
  30. 5.1 Introduction / p64 (0072.jp2)
  31. 5.2 Hybrid Approach / p65 (0073.jp2)
  32. 5.3 Accelerating Fault Simulation / p66 (0074.jp2)
  33. 5.4 Experimental Results / p75 (0083.jp2)
  34. 5.5 Conclusion / p78 (0086.jp2)
  35. 6.Concluding Remarks and Future works / p79 (0087.jp2)
  36. Acknowledgement / p82 (0090.jp2)
  37. References / p84 (0092.jp2)
  38. List of Publications by the Author / p92 (0100.jp2)
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Codes

  • NII Article ID (NAID)
    500000084392
  • NII Author ID (NRID)
    • 8000000084604
  • DOI(NDL)
  • Text Lang
    • und
  • NDLBibID
    • 000000248706
  • Source
    • Institutional Repository
    • NDL ONLINE
    • NDL Digital Collections

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