Studies on functional information extraction from logic circuits 論理回路の機能情報抽出に関する研究
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Bibliographic Information
- Title
-
Studies on functional information extraction from logic circuits
- Other Title
-
論理回路の機能情報抽出に関する研究
- Author
-
大村, 昌彦
- Author(Another name)
-
オオムラ, マサヒコ
- University
-
京都大学
- Types of degree
-
博士 (工学)
- Grant ID
-
甲第5452号
- Degree year
-
1993-05-24
Note and Description
博士論文
Table of Contents
- 論文目録 / (0001.jp2)
- Abstract / p1 (0004.jp2)
- Contents / p3 (0005.jp2)
- 1 Introduction / p1 (0007.jp2)
- 1.1 Backgrounds / p1 (0007.jp2)
- 1.2 Outline of the Thesis / p4 (0009.jp2)
- 2 What is Functional Information Extraction? / p7 (0010.jp2)
- 2.1 Overview of Functional Information Extraction / p7 (0010.jp2)
- 2.2 Applications / p9 (0011.jp2)
- 3 Representations of Functional Information / p13 (0013.jp2)
- 3.1 Representations of Logic Functions / p13 (0013.jp2)
- 3.2 Binary Decision Diagrams / p14 (0014.jp2)
- 3.3 Definitions / p18 (0016.jp2)
- 4 Extraction of Logic Functions from Combinational Circuits / p19 (0016.jp2)
- 4.1 Introduction / p19 (0016.jp2)
- 4.2 How to Extract Function Tables / p20 (0017.jp2)
- 4.3 Experimental Results / p24 (0019.jp2)
- 5 Extraction of Arithmetic Functions / p29 (0021.jp2)
- 5.1 Introduction / p29 (0021.jp2)
- 5.2 Extraction of Arithmetic Operations / p31 (0022.jp2)
- 5.3 Iterative Forms / p39 (0026.jp2)
- 5.4 Extraction of Iterative Forms / p49 (0031.jp2)
- 5.5 Experimental Results / p54 (0034.jp2)
- 6 Function Extraction from Synchronous Sequential Circuits / p61 (0037.jp2)
- 6.1 Overviews / p61 (0037.jp2)
- 6.2 Fundamental Techniques / p62 (0038.jp2)
- 6.3 Extraction from Circuits with Control Registers / p64 (0039.jp2)
- 6.4 Extraction from Circuits with Data Registers / p67 (0040.jp2)
- 6.5 Experimental Results / p73 (0043.jp2)
- 7 FINES:A Prototype System / p75 (0044.jp2)
- 7.1 Introduction / p75 (0044.jp2)
- 7.2 Components of FINES / p76 (0045.jp2)
- 7.3 Performance of the System / p81 (0047.jp2)
- 8 Applications-Design Verification / p83 (0048.jp2)
- 8.1 Introduction / p83 (0048.jp2)
- 8.2 Verification of Logic Designs / p84 (0049.jp2)
- 8.3 Behavioral Verification of CPUs / p86 (0050.jp2)
- 8.4 Examples / p95 (0054.jp2)
- 9 Conclusions / p101 (0057.jp2)
- Bibliography / p105 (0059.jp2)
- Acknowledgement / p111 (0062.jp2)
- List of Publications by the Author / p113 (0063.jp2)