Study of circuit design for high-speed A-to-D conversion LSI 高速A/D変換LSI設計法の研究

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Author

    • 脇本, 力 ワキモト, ツトム

Bibliographic Information

Title

Study of circuit design for high-speed A-to-D conversion LSI

Other Title

高速A/D変換LSI設計法の研究

Author

脇本, 力

Author(Another name)

ワキモト, ツトム

University

東京工業大学

Types of degree

博士 (工学)

Grant ID

乙第2375号

Degree year

1992-07-31

Note and Description

博士論文

Table of Contents

  1. 論文目録 / (0002.jp2)
  2. CONTENTS / p1 (0004.jp2)
  3. CHAPTER1 INTRODUCTION / p1 (0006.jp2)
  4. CHAPTER2 REVIEW OF HIGH-SPEED A-TO-D CONVERSION LSI / p6 (0009.jp2)
  5. 2.1 Introduction / p7 (0009.jp2)
  6. 2.2 Integrated Circuit Technology / p7 (0009.jp2)
  7. 2.3 Wide-Band Amplifier / p13 (0012.jp2)
  8. 2.4 High-Speed A-to-D Conversion LST / p18 (0015.jp2)
  9. CHAPTER3 WIDE-BAND AMPLIFIER / p23 (0017.jp2)
  10. 3.1 Introduction / p24 (0018.jp2)
  11. 3.2 Practical Factor Limiting Bandwidth of Low-Power Amplifier using High-Speed Transistors / p24 (0018.jp2)
  12. 3.3 Basic Concept of Parasitic Capacitance Compensation Technique / p29 (0020.jp2)
  13. 3.4 Circuit Design Consideration / p32 (0022.jp2)
  14. 3.5 Experimental Results / p40 (0026.jp2)
  15. 3.6 GaAsMESFET Wide-Band Amplifier / p46 (0029.jp2)
  16. 3.7 Conclusion / p59 (0035.jp2)
  17. CHAPTER4 HIGH-SPEED HIGH-RESOLUTION SAMPLE-AND-HOLD CIRCUIT / p62 (0037.jp2)
  18. 4.1 Introduction / p63 (0037.jp2)
  19. 4.2 Factors Limiting the Performance / p64 (0038.jp2)
  20. 4.3 Circuit Techniques to suppress Error Sources / p72 (0042.jp2)
  21. 4.4 Performance Estimation / p80 (0046.jp2)
  22. 4.5 Conclusion / p87 (0049.jp2)
  23. CHAPTER5 FLASH A-TO-D CONVERTER / p89 (0050.jp2)
  24. 5.1 Introduction / p90 (0051.jp2)
  25. 5.2 Factors Limiting the Speed and Accuracy / p91 (0051.jp2)
  26. 5.3 Circuit Design Consideration of the Comparator / p92 (0052.jp2)
  27. 5.4 Encoder Circuit / p102 (0057.jp2)
  28. 5.5 Process Technology / p106 (0059.jp2)
  29. 5.6 Experimental Results / p108 (0060.jp2)
  30. 5.7 High-Speed Comparator Employing Parasitic Junction Capacitance Compensation Technique / p114 (0063.jp2)
  31. 5.8 Low-Distortion Input Buffers / p116 (0064.jp2)
  32. 5.9 New Logic Gate to Suppress the Error Caused by Meta-Stable State / p120 (0066.jp2)
  33. 5.10 Conclusion / p126 (0069.jp2)
  34. CHAPTER6 CONCLUSION / p128 (0070.jp2)
  35. PUBLISHED PAPERS / p132 (0072.jp2)
  36. ACKNOWLEDGMENTS / p136 (0074.jp2)
2access

Codes

  • NII Article ID (NAID)
    500000097040
  • NII Author ID (NRID)
    • 8000000097268
  • DOI(NDL)
  • NDLBibID
    • 000000261354
  • Source
    • NDL ONLINE
    • NDL Digital Collections

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