Two-dimensional fringing effects of scaled-down MOS field effect transistors 縮小したMOS電界効果トランジスタの二次元周辺効果
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著者
書誌事項
- タイトル
-
Two-dimensional fringing effects of scaled-down MOS field effect transistors
- タイトル別名
-
縮小したMOS電界効果トランジスタの二次元周辺効果
- 著者名
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岩井, 洋, 1949-
- 著者別名
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イワイ, ヒロシ
- 学位授与大学
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東京大学
- 取得学位
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博士 (工学)
- 学位授与番号
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乙第10641号
- 学位授与年月日
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1992-03-16
注記・抄録
博士論文
identifier:oai:t2r2.star.titech.ac.jp:99001618
目次
- CONTENTS / p9 (0006.jp2)
- 1 Introduction / p1 (0013.jp2)
- 1.1 The background and motive of this study / p1 (0013.jp2)
- 1.2 Problems to be solved and contents of this thesis / p13 (0019.jp2)
- 2 The on-chip capacitance measurement technique for diffused and other internal lines in VLSI / p21 (0023.jp2)
- 2.1 Introduction / p21 (0023.jp2)
- 2.2 Principle and procedure of measurement / p25 (0025.jp2)
- 2.3 Layout of the test circuits on a chip / p29 (0027.jp2)
- 2.4 Experiment and results / p33 (0029.jp2)
- 2.5 Discussions / p37 (0031.jp2)
- 2.6 Summary and conclusion of Chapter 2 / p38 (0032.jp2)
- 2.7 References for Chapter 2 / p39 (0032.jp2)
- 3 Characteristics and problems on the scaled-down LOCOS isolation structure / p41 (0033.jp2)
- 3.1 Introduction / p41 (0033.jp2)
- 3.2 Test device fabrication / p45 (0035.jp2)
- 3.3 Diffused line capacitance / p45 (0035.jp2)
- 3.4 Narrow-channel effect on threshold voltage of MOS transistor / p52 (0039.jp2)
- 3.5 Threshold voltage of field parasitic MOSFET and junction breakdown voltage / p55 (0040.jp2)
- 3.6 Discussion on the scaling-down of isolation / p55 (0040.jp2)
- 3.7 Summary and conclusions of Chapter 3 / p60 (0043.jp2)
- 3.8 References for Chapter 3 / p62 (0044.jp2)
- 4 Analysis for suppression of anomalous subthreshold drain current in short-channel MOSFET by two-dimensional device simulation / p65 (0045.jp2)
- 4.1 Introduction / p65 (0045.jp2)
- 4.2 Two-dimensional numerical analysis / p69 (0047.jp2)
- 4.3 Origins of the punch-through current and reciprocal slope for the log[数式]-[数式] characteristic / p72 (0049.jp2)
- 4.4 Suppression of the punch-through current by a deep ion-implanted structure / p75 (0050.jp2)
- 4.5 Discussions / p79 (0052.jp2)
- 4.6 Summary and conclusions of Chapter 4 / p81 (0053.jp2)
- 4.7 References for Chapter 4 / p82 (0054.jp2)
- 5 The small-geometry MOSFET capacitance measurement technique and observed short- and narrow-channel effects / p85 (0055.jp2)
- 5.1 Introduction / p85 (0055.jp2)
- 5.2 Principle of measurements / p87 (0056.jp2)
- 5.3 Circuits and layout configuration / p91 (0058.jp2)
- 5.4 Measurement procedure / p96 (0061.jp2)
- 5.5 Result 1(large and small device measurements and its resolution) / p108 (0067.jp2)
- 5.6 Result 2(observed short-channel effects) / p113 (0069.jp2)
- 5.7 Result 3(observed narrow-channel effects) / p121 (0073.jp2)
- 5.8 Discussions / p123 (0074.jp2)
- 5.9 Summary and conclusions of Chapter 5 / p132 (0079.jp2)
- 5.10 References for Chapter 5 / p134 (0080.jp2)
- 6 Analysis of the short-channel effect on MOSFET capacitances / p137 (0081.jp2)
- 6.1 Introduction / p137 (0081.jp2)
- 6.2.Method for obtaining capacitances using two-dimensional simulation / p141 (0083.jp2)
- 6.3.MOSFET capacitance simulation and results / p146 (0086.jp2)
- 6.4.Analysis of simulated results / p151 (0088.jp2)
- 6.5 Discussion / p171 (0098.jp2)
- 6.6 Summary and conclusions of Chapter 6 / p173 (0099.jp2)
- 6.7 References for Chapter 6 / p174 (0100.jp2)
- 7 Summary and conclusions / p177 (0101.jp2)