Array multiplication schemes for digital signal processors デジタルシグナルプロセッサ用アレイ型乗算機構
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Bibliographic Information
- Title
-
Array multiplication schemes for digital signal processors
- Other Title
-
デジタルシグナルプロセッサ用アレイ型乗算機構
- Author
-
Islam, Farhad Fuad
- Author(Another name)
-
イスラム, ファルハド ファド
- University
-
京都大学
- Types of degree
-
博士 (工学)
- Grant ID
-
甲第5489号
- Degree year
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1993-07-23
Note and Description
博士論文
Table of Contents
- 論文目録 / (0001.jp2)
- Contents / p5 (0006.jp2)
- Abstract / p1 (0004.jp2)
- Contents / p5 (0006.jp2)
- 1 Introduction / (0008.jp2)
- 1.1 Background / p1 (0008.jp2)
- 1.2 Review of Array Multiplier-Accumulator(MAC) / p3 (0009.jp2)
- 1.3 Pipelining an Array MAC / p9 (0012.jp2)
- 1.4 Outline of Thesis / p12 (0014.jp2)
- 1.5 Definitions / p13 (0014.jp2)
- 2 Array Multiplication by Multiple Wave Front(MWF)Computation / p17 (0016.jp2)
- 2.1 Introduction / p17 (0016.jp2)
- 2.2 Hardware Algorithm for MWF Computation / p19 (0017.jp2)
- 2.3 Architecture Realizing MWF Computation / p22 (0019.jp2)
- 2.4 Comparison with Some Other Architectures / p30 (0023.jp2)
- 2.5 Remarks and Discussions / p40 (0028.jp2)
- 3 Multiple Wave Front Computation in Merged Array Multiplication / p45 (0030.jp2)
- 3.1 Introduction / p45 (0030.jp2)
- 3.2 Some Conventional Hardware Algorithms for MultiplicationAccumulation / p47 (0031.jp2)
- 3.3 Architecture for MWF Merged Array Multiplier / p52 (0034.jp2)
- 3.4 Analytic Comparison of Different Architectures / p57 (0036.jp2)
- 3.5 Experimental Verification of Analytic Comparisons / p62 (0039.jp2)
- 3.6 Remarks and Discussions / p67 (0041.jp2)
- 4 Area Efficient Multiplier Accumulator for High Speed Image Filtering / p69 (0042.jp2)
- 4.1 Introduction / p69 (0042.jp2)
- 4.2 Boundary Conditions of MAC / p72 (0044.jp2)
- 4.3 Proposed Hardware Algorithm / p74 (0045.jp2)
- 4.4 Example of Architecture Realizing Proposed Hardware Algorithm / p84 (0050.jp2)
- 4.5 Remarks and Discussions / p94 (0055.jp2)
- 5 Theory of Unified Multipliers / p97 (0056.jp2)
- 5.1 Introduction / p97 (0056.jp2)
- 5.2 A Generalized Theory for Multiplier Architecture / p98 (0057.jp2)
- 5.3 Unifying Traditional Array and Wallace Multipliers / p104 (0060.jp2)
- 5.4 Module Generation of Generalized Multipliers / p105 (0060.jp2)
- 5.5 Remarks and Discussions / p108 (0062.jp2)
- 6 Conclusions / p109 (0062.jp2)
- Bibliography / p113 (0064.jp2)
- Acknowledgement / p119 (0067.jp2)
- List of Major Symbols and Abbreviations / p121 (0068.jp2)
- List of Figures / p127 (0071.jp2)
- List of Publications by the Author / p131 (0073.jp2)