Design for multiple-valued logic networks and its fault tolerances

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博士論文

資料形態 : テキストデータプレーンテキスト

コレクション : 国立国会図書館デジタルコレクション > デジタル化資料 > 博士論文

Contents
Introduction
I Multiple-Valued PLA's and Its Fault Tolerances
1 A Fault Model for Multiple-Valued PLA's and Its Equivalences
1.1 Introduction
1.2 Definitions
1.3 Stuck-at Fault and Fault on Literal Generator
1.4 Bridging Fault
1.5 Conclusions
2 A Method of Test Pattern Generation for Multiple-Valued PLA's
2.1 Introduction
2.2 Preliminaries
2.3 Basis of ETPG for MV-PLA's
2.4 ETPG for a multiple-valued function
2.5 Conclusion
3 On Multiple-Valued Separable Unordered Codes
3.1 Introduction
3.2 On Multiple-Valued Unordered Codes
3.3 Multiple-Valued Separable Balanced Codes
3.4 Conclusions
II New Design Techniques for Finite State Machines
4 State Assignment for p-Valued Sequential Machines
4.1 Introduction
4.2 Sequential Machines and State Assignments
4.3 Algorithm of State Assignment
4.4 Experiments on Computer
4.5 Conclusions
5 An Optimum Half-Hot Code Assignment Algorithm for Input Encoding and Its Application to Finite State Machines
5.1 Introduction
5.2 Background and Definitions
5.3 HHC Optimum Input Encoding Algorithm
5.4 Experimental Results
5.5 Conclusions
Conclusions
Acknowledgments
Author's Papaers Concerning the Dissertation