Circuit design technologies for high-performance DRAMs 高性能DRAM用回路設計技術に関する研究
Access this Article
Search this Article
Author
Bibliographic Information
- Title
-
Circuit design technologies for high-performance DRAMs
- Other Title
-
高性能DRAM用回路設計技術に関する研究
- Author
-
砂永, 登志男
- Author(Another name)
-
スナガ, トシオ
- University
-
京都大学
- Types of degree
-
博士 (工学)
- Grant ID
-
乙第9211号
- Degree year
-
1996-03-23
Note and Description
博士論文
Table of Contents
- 論文目録 / (0001.jp2)
- TABLE OF CONTENTS / p2 (0005.jp2)
- ACKNOWLEDGMENT / p1 (0004.jp2)
- TABLE OF CONTENTS / p2 (0005.jp2)
- LIST OF ABBREVIATIONS / p4 (0006.jp2)
- ABSTRACT / p5 (0006.jp2)
- CHAPTER1.INTRODUCTION / p1 (0007.jp2)
- CHAPTER2.DRAM SPEED LIMITATIONS / p9 (0011.jp2)
- 2.1 Introduction / p9 (0011.jp2)
- 2.2 Principle of DRAM Operation / p10 (0012.jp2)
- 2.3 DRAM Timing Analysis / p13 (0013.jp2)
- 2.4 Scaling Rules / p15 (0014.jp2)
- 2.5 DRAM Cell Scaling / p17 (0015.jp2)
- 2.6 Array Circuit Speed / p21 (0017.jp2)
- 2.7 Peripheral Circuit Speed / p25 (0019.jp2)
- 2.8 Technology Comparisons of DRAM and Logic Chips / p28 (0021.jp2)
- 2.9 Conclusion / p34 (0024.jp2)
- PART ONE GENERAL-PURPOSE DRAMs / (0025.jp2)
- CHAPTER3.HIGH-SPEED DRAM / p39 (0026.jp2)
- 3.1 Introduction / p39 (0026.jp2)
- 3.2 Design Approach / p40 (0027.jp2)
- 3.3 Process Technology and Chip Description / p41 (0027.jp2)
- 3.4 Short-Signal-Path Architecture / p45 (0029.jp2)
- 3.5 Sensing Circuit / p47 (0030.jp2)
- 3.6 Measurement Results / p54 (0034.jp2)
- 3.7 Conclusion / p58 (0036.jp2)
- CHAPTER4.HIGH-BANDWIDTH DRAM / p61 (0037.jp2)
- 4.1 Introduction / p61 (0037.jp2)
- 4.2 High-Bandwidth Circuit Overview / p62 (0038.jp2)
- 4.3 Data Path Circuit Design / p64 (0039.jp2)
- 4.4 Performance Evaluation / p71 (0042.jp2)
- 4.5 16-Mb SDRAM Description / p75 (0044.jp2)
- 4.6 Chip Characteristics / p79 (0046.jp2)
- 4.7 Conclusion / p83 (0048.jp2)
- CHAPTER5.BURST MODE COMPATIBLE HIGH-SPEED SENSING CIRCUIT / p85 (0049.jp2)
- 5.1 Introduction / p85 (0049.jp2)
- 5.2 Review of High-Speed Sensing Circuit / p86 (0050.jp2)
- 5.3 Basic Design Concept / p88 (0051.jp2)
- 5.4 Block Diagram / p90 (0052.jp2)
- 5.5 Circuit Design / p93 (0053.jp2)
- 5.6 Simulation / p99 (0056.jp2)
- 5.7 Circuit Characteristics / p100 (0057.jp2)
- 5.8 Conclusion / p102 (0058.jp2)
- PART TWO APPLICATION-SPECIFIC DRAMs / (0059.jp2)
- CHAPTER6.SYSTEM INTERFACE / p107 (0060.jp2)
- 6.1 Introduction / p107 (0060.jp2)
- 6.2 ROM Chip Performance Issues / p108 (0061.jp2)
- 6.3 4-Mb ROM Chip Description / p109 (0061.jp2)
- 6.4 Address Increment Circuit / p113 (0063.jp2)
- 6.5 ROM Operations / p117 (0065.jp2)
- 6.6 Measurement Results / p124 (0069.jp2)
- 6.7 ROM System Interface Application to DRAMs / p124 (0069.jp2)
- 6.8 Conclusion / p131 (0072.jp2)
- CHAPTER7.GRAPHICS DRAM / p133 (0073.jp2)
- 7.1 Introduction / p133 (0073.jp2)
- 7.2 Graphics Application Requirements / p134 (0074.jp2)
- 7.3 Process Technology / p136 (0075.jp2)
- 7.4 Chip Features and Functions / p138 (0076.jp2)
- 7.5 Chip Organization / p140 (0077.jp2)
- 7.6 Circuits / p144 (0079.jp2)
- 7.7 Characteristics / p149 (0081.jp2)
- 7.8 Graphics Performance Evaluation / p152 (0083.jp2)
- 7.9 Conclusion / p153 (0083.jp2)
- CHAPTER8.DRAM MACRO / p155 (0084.jp2)
- 8.1 Introduction / p155 (0084.jp2)
- 8.2 Strategic Approaches for Technologies and Applications / p156 (0085.jp2)
- 8.3 Merged Process Technology / p158 (0086.jp2)
- 8.4 DRAM Macro Description / p161 (0087.jp2)
- 8.5 Characteristics / p172 (0093.jp2)
- 8.6 ASIC Applications / p177 (0095.jp2)
- 8.7 Conclusion / p182 (0098.jp2)
- CHAPTER9.DRAM AND LOGIC INTEGRATION / p185 (0099.jp2)
- 9.1 Introduction / p185 (0099.jp2)
- 9.2 Process Technology / p187 (0100.jp2)
- 9.3 Chip Description / p188 (0101.jp2)
- 9.4 Characteristics / p194 (0104.jp2)
- 9.5 Architecture Perspective for Future Technologies / p195 (0104.jp2)
- 9.6 Conclusion / p202 (0108.jp2)
- CHAPTER10.SUMMARY AND CONCLUSIONS / p205 (0109.jp2)
- REFERENCES / p211 (0112.jp2)
