Studies on low power technologies for battery-operated semiconductor random access memories バッテリー駆動用半導体メモリの低消費電力化技術に関する研究

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著者

    • 山内, 寛行 ヤマウチ, ヒロユキ

書誌事項

タイトル

Studies on low power technologies for battery-operated semiconductor random access memories

タイトル別名

バッテリー駆動用半導体メモリの低消費電力化技術に関する研究

著者名

山内, 寛行

著者別名

ヤマウチ, ヒロユキ

学位授与大学

九州大学

取得学位

博士 (工学)

学位授与番号

乙第6497号

学位授与年月日

1997-07-28

注記・抄録

博士論文

目次

  1. ABSTRACT / p1 (0003.jp2)
  2. ACKNOWLEDGMENTS / p3 (0004.jp2)
  3. A TABLE OF CONTENTS / p1 (0005.jp2)
  4. A List of Figures and Tables / p5 (0007.jp2)
  5. A List of Technical Terms and Symbols / p11 (0010.jp2)
  6. CHAPTER-1 Introduction / p16 (0013.jp2)
  7. 1-1 Backgrounds / p16 (0013.jp2)
  8. 1-2 Semiconductor Memories / p22 (0016.jp2)
  9. 1-3 Power Saving Requirements in Memory Systems / p26 (0018.jp2)
  10. 1-4 Technology Trend for Low Power Memory System / p31 (0020.jp2)
  11. 1-5 Purpose and Significance of This Study / p38 (0024.jp2)
  12. 1-6 Constitution of This Paper / p41 (0025.jp2)
  13. References / p43 (0026.jp2)
  14. CHAPTER-2 Charge Recycling Data Transfer / p46 (0028.jp2)
  15. 2-1 Introduction / p46 (0028.jp2)
  16. 2-2 Concept of Charge Recycling Bus(CRB) Architecture / p48 (0029.jp2)
  17. 2-3 Principle of CRB Operation / p54 (0032.jp2)
  18. 2-4 Circuit Configuration of CRB / p58 (0034.jp2)
  19. 2-5 Circuit Operation and Performance / p63 (0036.jp2)
  20. 2-6 Bus Capacitance Imbalances Issues / p67 (0038.jp2)
  21. 2-7 Power-on State Issue and Noise Issue / p70 (0040.jp2)
  22. 2-8 Conclusion / p72 (0041.jp2)
  23. References / p72 (0041.jp2)
  24. CHAPTER-3 Signal-Swing Suppressing Time-Multiplexed Differential Data-Transfer Scheme / p73 (0041.jp2)
  25. 3-1 Introduction / p73 (0041.jp2)
  26. 3-2 Background and Target / p75 (0042.jp2)
  27. 3-3 Concept of Time Multiplexed Differential data transfer(TMD)scheme / p79 (0044.jp2)
  28. 3-4 Low Power Strategy using TMD Combined with CRB(TM-CRB) / p84 (0047.jp2)
  29. 3-5 Power and Area Comparisons / p89 (0049.jp2)
  30. 3-6 Conclusion / p95 (0052.jp2)
  31. References / p95 (0052.jp2)
  32. CHAPTER-4 Data Retention Power Saving for DRAM's / p96 (0053.jp2)
  33. 4-1 Introduction / p96 (0053.jp2)
  34. 4-2 Extending DRAM Data Retention Time / p98 (0054.jp2)
  35. 4-3 Extension of DRAM Refresh Interval / p103 (0056.jp2)
  36. 4-4 DC Retention Current / p110 (0060.jp2)
  37. 4-5 Low Power Performance / p115 (0062.jp2)
  38. 4-6 Conclusion / p118 (0064.jp2)
  39. References / p118 (0064.jp2)
  40. CHAPTER-5 Circuit Technology for High-Speed Battery-Operated DRAM's / p119 (0064.jp2)
  41. 5-1 Introduction / p119 (0064.jp2)
  42. 5-2 Redundancy Architecture / p121 (0065.jp2)
  43. 5-3 A Quasi-static Signal Sensing Amplifier / p123 (0066.jp2)
  44. 5-4 Gate-Isolated Sense Amplifier(GISA)with Low Threshold Voltage / p129 (0069.jp2)
  45. 5-5 0.5μm CMOS 16Mbit DRAM Chip Features / p133 (0071.jp2)
  46. 5-6 Conclusion / p138 (0074.jp2)
  47. References / p138 (0074.jp2)
  48. CHAPTER-6 Circuit Technology for High-Speed Battery-Operated SRAM's / p140 (0075.jp2)
  49. 6-1 Introduction / p140 (0075.jp2)
  50. 6-2 Deep Sub-IV High-Speed SRAM Cell Strategy / p146 (0078.jp2)
  51. 6-3 Power Comparisons and Discussions / p157 (0083.jp2)
  52. 6-4 Conclusion / p163 (0086.jp2)
  53. References / p163 (0086.jp2)
  54. CHAPTER-7 Conclusion / p165 (0087.jp2)
  55. 7-1 Conclusion of This Study / p165 (0087.jp2)
  56. 7-2 Technical Prospect / p167 (0088.jp2)
  57. Bibliography Written by the Author / p170 (0090.jp2)
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各種コード

  • NII論文ID(NAID)
    500000151812
  • NII著者ID(NRID)
    • 8000001068749
  • DOI(NDL)
  • NDL書誌ID
    • 000000316126
  • データ提供元
    • NDL ONLINE
    • NDLデジタルコレクション
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