Construction of communication and storage systems with high security and high reliability

この論文をさがす

著者

    • 佐竹, 賢治 サタケ, ケンジ

書誌事項

タイトル

Construction of communication and storage systems with high security and high reliability

著者名

佐竹, 賢治

著者別名

サタケ, ケンジ

学位授与大学

京都工芸繊維大学

取得学位

博士 (工学)

学位授与番号

甲第144号

学位授与年月日

1997-03-25

注記・抄録

博士論文

目次

  1. Preface / p1 (0004.jp2)
  2. Contents / p3 (0005.jp2)
  3. List of Figures / p7 (0007.jp2)
  4. Chapter 1 Introduction / p1 (0008.jp2)
  5. Chapter 2 Fast Cryptosystem / p7 (0011.jp2)
  6. 2.1 Introduction / p7 (0011.jp2)
  7. 2.2 Preliminaries / p8 (0012.jp2)
  8. 2.3 Fast Method of Calculating Modular Multiplication / p10 (0013.jp2)
  9. 2.4 Generating Composite Number n / p18 (0017.jp2)
  10. 2.5 Applying the Proposed Method to RSA-type Cryptosystem / p22 (0019.jp2)
  11. 2.6 Conclusion / p25 (0020.jp2)
  12. Chapter 3 Hard-Decision Decoding for Superimposed Codes / p27 (0021.jp2)
  13. 3.1 Introduction / p27 (0021.jp2)
  14. 3.2 Preliminaries / p28 (0022.jp2)
  15. 3.3 Optimum Combination of Codes / p32 (0024.jp2)
  16. 3.4 Conclusion / p36 (0026.jp2)
  17. Chapter 4 High-order Superimposed Codes / p37 (0026.jp2)
  18. 4.1 Introduction / p37 (0026.jp2)
  19. 4.2 Construction of High-order Superimposed Codes / p38 (0027.jp2)
  20. 4.3 Decoding Method and Channel Model / p40 (0028.jp2)
  21. 4.4 Decoding Error Probability / p44 (0030.jp2)
  22. 4.5 Optimum Combination of BCH Codes / p45 (0030.jp2)
  23. 4.6 Applicable channel / p50 (0033.jp2)
  24. 4.7 Conclusion / p54 (0035.jp2)
  25. Chapter 5 Soft-Decision Decoding for Superimposed Codes / p55 (0035.jp2)
  26. 5.1 Introduction / p55 (0035.jp2)
  27. 5.2 Weaker Codes / p57 (0036.jp2)
  28. 5.3 Imposed Codes / p61 (0038.jp2)
  29. 5.4 Performance of Superimposed Codes / p65 (0040.jp2)
  30. 5.5 Decoding Complexity / p68 (0042.jp2)
  31. 5.6 Conclusion / p69 (0042.jp2)
  32. Chapter 6 Conclusion / p71 (0043.jp2)
  33. Appendix A / p73 (0044.jp2)
  34. A.1 Proof of Theorem 2.1 / p73 (0044.jp2)
  35. A.2 Proof of Theorem 2.2 / p74 (0045.jp2)
  36. Appendix B / p79 (0047.jp2)
  37. B.1 Circuit Scale of Superimposed Codes / p79 (0047.jp2)
  38. Appendix C / p81 (0048.jp2)
  39. C.1 Number of Check Symbols for High Rates / p81 (0048.jp2)
  40. Appendix D / p83 (0049.jp2)
  41. D.1 Proof of Equation 5.9 / p83 (0049.jp2)
  42. Acknowledgments / p87 (0051.jp2)
  43. References / p89 (0052.jp2)
3アクセス

各種コード

  • NII論文ID(NAID)
    500000151943
  • NII著者ID(NRID)
    • 8000001068870
  • DOI(NDL)
  • NDL書誌ID
    • 000000316257
  • データ提供元
    • NDL-OPAC
    • NDLデジタルコレクション
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