Synthesis of asynchronous VLSI circuits from signal transition graph specifications 信号遷移グラフ仕様による非同期式VLSI回路の合成
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Bibliographic Information
- Title
-
Synthesis of asynchronous VLSI circuits from signal transition graph specifications
- Other Title
-
信号遷移グラフ仕様による非同期式VLSI回路の合成
- Author
-
朴, 星範
- Author(Another name)
-
パク, ソンボム
- University
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東京工業大学
- Types of degree
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博士 (学術)
- Grant ID
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甲第3339号
- Degree year
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1996-09-30
Note and Description
博士論文
Table of Contents
- 論文目録 / (0001.jp2)
- Contents / p7 (0010.jp2)
- Abstract / p3 (0006.jp2)
- Acknowledgements / p4 (0007.jp2)
- 1 Introduction / p1 (0019.jp2)
- 1.1 Motivation / p1 (0019.jp2)
- 1.2 Environment and circuit models / p3 (0021.jp2)
- 1.3 Previous Work to Asynchronous Design / p6 (0024.jp2)
- 1.4 Contributions of the Thesis / p10 (0028.jp2)
- 1.5 Overview of the Thesis / p10 (0028.jp2)
- 2 Signal Transition Graph Specifications / p13 (0031.jp2)
- 2.1 Petri nets / p13 (0031.jp2)
- 2.2 Signal Transition Graphs / p15 (0033.jp2)
- 2.3 Region / p19 (0037.jp2)
- 3 Hazard Consideration and Circuit Structure / p21 (0039.jp2)
- 3.1 Timing and technology assumptions / p21 (0039.jp2)
- 3.2 Hazard consideration / p22 (0040.jp2)
- 3.3 Generalized Circuit Structure / p26 (0044.jp2)
- 3.4 Speed-independent Signal Network / p28 (0046.jp2)
- 4 Synthesis based on Lock Relations / p31 (0049.jp2)
- 4.1 Introduction / p31 (0049.jp2)
- 4.2 Previous Work / p31 (0049.jp2)
- 4.3 Circuit Structure / p32 (0050.jp2)
- 4.4 Speed-independent Implementation / p33 (0051.jp2)
- 4.5 Optimization / p41 (0059.jp2)
- 4.6 Experimental Results / p46 (0064.jp2)
- 4.7 Conclusions / p48 (0066.jp2)
- 5 Synthesis based on State Assignment / p51 (0069.jp2)
- 5.1 Introduction / p51 (0069.jp2)
- 5.2 Previous Works / p52 (0070.jp2)
- 5.3 State assignment at the STG domain / p53 (0071.jp2)
- 5.4 Circuit Structure / p56 (0074.jp2)
- 5.5 Speed-independent implementation / p56 (0074.jp2)
- 5.6 Extension to non-persistent STGs / p59 (0077.jp2)
- 5.7 Optimization / p61 (0079.jp2)
- 5.8 Experimental Results / p64 (0082.jp2)
- 5.9 Conclusions / p69 (0087.jp2)
- 6 Assist:an asynchronous synthesis system / p71 (0089.jp2)
- 6.1 Running Assist / p72 (0090.jp2)
- 6.2 Input specifications / p72 (0090.jp2)
- 6.3 Synthesis Examples:Persistent single-cycle STGs / p75 (0093.jp2)
- 6.4 Synthesis Examples:Persistent multi-cycle STGs / p84 (0102.jp2)
- 6.5 Synthesis Examples:Persistent STGs with choice operations / p86 (0104.jp2)
- 6.6 Synthesis Examples:Non-persistent STGs / p99 (0117.jp2)
- 7 Conclusions and Future Work / p103 (0121.jp2)