Study on multiple states extraction using one-dimensional nonlinear CMOS map circuit

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著者

    • 朱, 俊騏 シュ, シュンキ

書誌事項

タイトル

Study on multiple states extraction using one-dimensional nonlinear CMOS map circuit

著者名

朱, 俊騏

著者別名

シュ, シュンキ

学位授与大学

上智大学

取得学位

博士 (工学)

学位授与番号

甲第190号

学位授与年月日

1998-03-31

注記・抄録

博士論文

目次

  1. Contents / p1 (0004.jp2)
  2. List of Figures / p4 (0006.jp2)
  3. 1.Introduction / p1 (0008.jp2)
  4. 1.1 Background of this Study / p2 (0009.jp2)
  5. 1.2 Structure of this Thesis / p5 (0010.jp2)
  6. References / p5 (0010.jp2)
  7. 2.One-Dimensional Nonlinear CMOS Map Circuit and Observation.Analysis of Chaos in its Direct Mapping System / p7 (0011.jp2)
  8. 2.1 Introduction / p8 (0012.jp2)
  9. 2.2 One-Dimensional Nonlinear CMOS Map Circuit / p8 (0012.jp2)
  10. 2.3 Construction of Direct Mapping System / p9 (0012.jp2)
  11. 2.4 Observation and Analysis of Internal States / p11 (0013.jp2)
  12. 2.5 Discussion / p16 (0016.jp2)
  13. 2.6 Concluding Remarks / p17 (0016.jp2)
  14. References / p17 (0016.jp2)
  15. 3.Multiple States Extraction (I) / p32 (0024.jp2)
  16. 3.1 Introduction / p33 (0024.jp2)
  17. 3.2 Circuit Construction / p33 (0024.jp2)
  18. 3.3 State Restriction with Non-uniform Quantization / p34 (0025.jp2)
  19. 3.4 Characteristics of Extracted Multiple-State Motion / p36 (0026.jp2)
  20. 3.5 Discussion / p38 (0027.jp2)
  21. 3.6 Concluding Remarks / p39 (0027.jp2)
  22. References / p40 (0028.jp2)
  23. 4.Effects of Nonlinear Quantization of Internal States Obtained from CMOS Map Circuit on Transfer Characteristics / p52 (0034.jp2)
  24. 4.1 Introduction / p53 (0034.jp2)
  25. 4.2 Experimental Procedure / p53 (0034.jp2)
  26. 4.3 Round-Trip Transfer Characteristic of Internal States in Time Series / p55 (0035.jp2)
  27. 4.4 Methodology of Nonlinear Quantization Extending Prediction of Internal States in Time Series / p56 (0036.jp2)
  28. 4.5 Application:Cryptosystem / p58 (0037.jp2)
  29. 4.6 Concluding Remarks / p60 (0038.jp2)
  30. References / p60 (0038.jp2)
  31. 5.Multiple States Extraction (II):64-State Cell / p69 (0042.jp2)
  32. 5.1 Introduction / p70 (0043.jp2)
  33. 5.2 Circuit Construction / p70 (0043.jp2)
  34. 5.3 Algorithm of Nonlinear State Filtering and Design of Nonlinear ADC and DAC / p71 (0043.jp2)
  35. 5.4 Extracted 64 States under Nonlinear Quantization / p74 (0045.jp2)
  36. 5.5 Discussion / p76 (0046.jp2)
  37. 5.6 Concluding Remarks / p76 (0046.jp2)
  38. References / p77 (0046.jp2)
  39. 6.Concluding Remarks / p91 (0053.jp2)
  40. 6.1 Progress of this Study / p91 (0053.jp2)
  41. 6.2 Future Research / p92 (0054.jp2)
  42. References / p93 (0054.jp2)
  43. Appendix:Logistic Map / p94 (0055.jp2)
  44. Acknowledgments / p102 (0059.jp2)
  45. List of Publications / p103 (0059.jp2)
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各種コード

  • NII論文ID(NAID)
    500000154441
  • NII著者ID(NRID)
    • 8000001093441
  • DOI(NDL)
  • NDL書誌ID
    • 000000318755
  • データ提供元
    • NDL-OPAC
    • NDLデジタルコレクション
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