Development of high-speed silicon devices and their design with advanced physical models 高速シリコンデバイスの開発とその設計の研究

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著者

    • 後藤, 広志 ゴトウ, ヒロシ

書誌事項

タイトル

Development of high-speed silicon devices and their design with advanced physical models

タイトル別名

高速シリコンデバイスの開発とその設計の研究

著者名

後藤, 広志

著者別名

ゴトウ, ヒロシ

学位授与大学

広島大学

取得学位

博士 (工学)

学位授与番号

乙第3169号

学位授与年月日

1999-02-10

注記・抄録

博士論文

目次

  1. Table of Contents / p5 (0006.jp2)
  2. Abstract / p2 (0003.jp2)
  3. Acknowledgments / p3 (0004.jp2)
  4. Chapter 1 Introduction / p1 (0010.jp2)
  5. 1.1 Motivation / p1 (0010.jp2)
  6. 1.2 Scope and Organization / p1 (0010.jp2)
  7. Chapter 2 Development of High-Speed Silicon Bipolar Devices / p4 (0012.jp2)
  8. 2.1 Historical Back Ground / p4 (0012.jp2)
  9. 2.2 Trench Isolation Techniques / p5 (0012.jp2)
  10. 2.3 Polysilicon Self-Aligned Structures / p19 (0019.jp2)
  11. 2.4 Physics-Based Bipolar Transistor Design / p37 (0028.jp2)
  12. Chapter 3 Performance Estimation of High-Speed Bipolar Device / p47 (0033.jp2)
  13. 3.1 Introduction / p47 (0033.jp2)
  14. 3.2 Strategy to Estimate ECL-Circuit Performance / p47 (0033.jp2)
  15. 3.3 Optimization of ECL-Circuit Performance / p54 (0037.jp2)
  16. 3.4 Favorable Silicon BJT Features and Its Limitation / p56 (0038.jp2)
  17. 3.5 Conclusion / p58 (0039.jp2)
  18. Chapter 4 Design Concept for High-Speed CMOS Device / p60 (0040.jp2)
  19. 4.1 Introduction / p60 (0040.jp2)
  20. 4.2 Requirements for High-Speed CMOS Device / p61 (0040.jp2)
  21. 4.3 Quarter and Subquarter Micron CMOS Technologies / p63 (0041.jp2)
  22. 4.4 Conclusion / p64 (0042.jp2)
  23. Chapter 5 Inverse Modeling Technique for MOSFET Design / p65 (0042.jp2)
  24. 5.1 Introduction / p65 (0042.jp2)
  25. 5.2 Inverse Modeling Procedure / p66 (0043.jp2)
  26. 5.3 Extraction of a Deep Submicron MOSFET Structure / p68 (0044.jp2)
  27. 5.4 Saturation Drain Current and Substrate Current / p77 (0048.jp2)
  28. 5.5 Device Characteristic Prediction / p79 (0049.jp2)
  29. 5.6 Conclusion / p80 (0050.jp2)
  30. Chapter 6 Carrier Transport in MOSFETs / p81 (0050.jp2)
  31. 6.1 Introduction / p81 (0050.jp2)
  32. 6.2 Modeling of Carrier Transport in MOSFETs / p82 (0051.jp2)
  33. 6.3 Impact Ionization in MOSFETs / p90 (0055.jp2)
  34. 6.4 Conclusion / p98 (0059.jp2)
  35. Chapter 7 Physics-Based MOSFET Design / p99 (0059.jp2)
  36. 7.1 Introduction / p99 (0059.jp2)
  37. 7.2 Hot Carrier Effects of nMOSFET / p100 (0060.jp2)
  38. 7.3 Physics-Based MOSFET Design / p104 (0062.jp2)
  39. 7.4 Conclusion / p106 (0063.jp2)
  40. Chapter 8 Conclusion / p107 (0063.jp2)
  41. 8.1 Summary / p107 (0063.jp2)
  42. 8.2 Future Work / p108 (0064.jp2)
  43. Bibliography / p110 (0065.jp2)
  44. List of Papers / p122 (0071.jp2)
6アクセス

各種コード

  • NII論文ID(NAID)
    500000185365
  • NII著者ID(NRID)
    • 8000000185647
  • DOI(NDL)
  • NDL書誌ID
    • 000000349679
  • データ提供元
    • NDL ONLINE
    • NDLデジタルコレクション
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