System level optimization techniques for low power VLSI design 低電力集積回路設計のためのシステムレベルにおける最適化手法
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著者
書誌事項
- タイトル
-
System level optimization techniques for low power VLSI design
- タイトル別名
-
低電力集積回路設計のためのシステムレベルにおける最適化手法
- 著者名
-
石原, 亨
- 著者別名
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イシハラ, トオル
- 学位授与大学
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九州大学
- 取得学位
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博士 (工学)
- 学位授与番号
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甲第5195号
- 学位授与年月日
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2000-03-27
注記・抄録
博士論文
Contents Abstract Contents 1 Introduction 2 Low Power System Design 3 Variable Voltage Scheduling 4 Programmable Power Management Architecture 5 Memory Power Optimization with Code Merging 6 Conclusions Acknowledgment Bibliography List of Publications by the Author
主1-参1
システム情報_情報工学
目次
- Contents / p5 (0005.jp2)
- Abstract / p1 (0003.jp2)
- Contents / p5 (0005.jp2)
- 1 Introduction / p1 (0007.jp2)
- 1.1 Background / p1 (0007.jp2)
- 1.2 Goal of This Research / p2 (0008.jp2)
- 1.3 Policy of This Research / p3 (0008.jp2)
- 1.4 Contributions of This Research / p4 (0009.jp2)
- 1.5 Organization of This Thesis / p6 (0010.jp2)
- 2 Low Power System Design / p7 (0010.jp2)
- 2.1 Power Dissipation Models / p7 (0010.jp2)
- 2.2 Optimization of Supply Voltage / p10 (0012.jp2)
- 2.3 Reducing the Switching Activity / p13 (0013.jp2)
- 2.4 Reducing the Frequently Switched Capacitance / p15 (0014.jp2)
- 2.5 Optimization of the Number of Execution Cycles / p16 (0015.jp2)
- 2.6 Summary / p19 (0016.jp2)
- 3 Variable Voltage Scheduling / p21 (0017.jp2)
- 3.1 Background / p21 (0017.jp2)
- 3.2 Basic Theorems on a Simple Model / p24 (0019.jp2)
- 3.3 Generalized Theorems on a More Realistic Model / p30 (0022.jp2)
- 3.4 ILP Formulation / p35 (0024.jp2)
- 3.5 A Voltage Scheduling Algorithm / p37 (0025.jp2)
- 3.6 Experimental Results / p39 (0026.jp2)
- 3.7 Summary / p42 (0028.jp2)
- 4 Programmable Power Management Architecture / p45 (0029.jp2)
- 4.1 Background / p45 (0029.jp2)
- 4.2 Reduction of Wasteful Power Consumption / p46 (0030.jp2)
- 4.3 The Power-Pro Architecture / p49 (0031.jp2)
- 4.4 Applications / p53 (0033.jp2)
- 4.5 Experimental Results / p56 (0035.jp2)
- 4.6 Simulation Results of Pilot Chip / p59 (0036.jp2)
- 4.7 Summary / p61 (0037.jp2)
- 5 Memory Power Optimization with Code Merging / p63 (0038.jp2)
- 5.1 Background / p63 (0038.jp2)
- 5.2 Motivations and Our Approach / p64 (0039.jp2)
- 5.3 Power Optimization with Object Code Merging / p70 (0042.jp2)
- 5.4 Experimental Results / p76 (0045.jp2)
- 5.5 Summary / p87 (0050.jp2)
- 6 Conclusions / p89 (0051.jp2)
- 6.1 Summary of Contributions / p89 (0051.jp2)
- 6.2 Future Directions / p91 (0052.jp2)
- Acknowledgment / p93 (0053.jp2)
- Bibliography / p95 (0054.jp2)
- List of Publications by the Author / p103 (0058.jp2)