Nonlinear co-channel interference cancellation technique for digital mobile communications ディジタル移動通信のための非線形同一チャネル干渉波キャンセル技術

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Author

    • 村田, 英一 ムラタ, ヒデカズ

Bibliographic Information

Title

Nonlinear co-channel interference cancellation technique for digital mobile communications

Other Title

ディジタル移動通信のための非線形同一チャネル干渉波キャンセル技術

Author

村田, 英一

Author(Another name)

ムラタ, ヒデカズ

University

京都大学

Types of degree

博士 (工学)

Grant ID

乙第10405号

Degree year

2000-03-23

Note and Description

博士論文

identifier:oai:t2r2.star.titech.ac.jp:99003395

Table of Contents

  1. 論文目録 (1コマ目)
  2. Contents/p1 (4コマ目)
  3. 1 Introduction/p1 (8コマ目)
  4. 1.1 Digital Wireless Communication Systems/p1 (8コマ目)
  5. 1.2 Cellular Systems/p2 (9コマ目)
  6. 1.3 Fading Channel/p2 (9コマ目)
  7. 1.4 Diversity Reception/p5 (10コマ目)
  8. 1.5 Equalization/p6 (11コマ目)
  9. 1.6 Nonlinear Interference Canceller/p7 (11コマ目)
  10. 1.7 Countermeasure for Ambiguity/p9 (12コマ目)
  11. 2 Trellis-coded Co-channel Interference Canceller/p13 (14コマ目)
  12. 2.1 System Description/p13 (14コマ目)
  13. 2.2 Trellis-coded Modulation/p14 (15コマ目)
  14. 2.3 Proposed Canceller/p21 (18コマ目)
  15. 2.4 Simulation Results/p24 (20コマ目)
  16. 2.5 Summary/p35 (25コマ目)
  17. 3 TCC with Reduced Complexity/p37 (26コマ目)
  18. 3.1 Introduction/p37 (26コマ目)
  19. 3.2 TCC with Reduced Complexity/p37 (26コマ目)
  20. 3.3 Simulation Results/p41 (28コマ目)
  21. 3.4 Comparison between M-algorithm and T-algorithm/p57 (36コマ目)
  22. 3.5 Summary/p60 (38コマ目)
  23. 4 TCC with Interleaving/p65 (40コマ目)
  24. 4.1 Introduction/p65 (40コマ目)
  25. 4.2 System Model/p66 (41コマ目)
  26. 4.3 Proposed Algorithm/p68 (42コマ目)
  27. 4.4 Simulation Results/p73 (44コマ目)
  28. 4.5 Summary/p82 (49コマ目)
  29. 5 Frequency Offset Compensation for TCC/p83 (49コマ目)
  30. 5.1 Introduction/p83 (49コマ目)
  31. 5.2 System Description/p84 (50コマ目)
  32. 5.3 Proposed Algorithm/p85 (50コマ目)
  33. 5.4 Simulation Results/p90 (53コマ目)
  34. 5.5 Summary/p95 (55コマ目)
  35. 6 Experimental Study/p97 (56コマ目)
  36. 6.1 130k-gate FPGA Implementation/p98 (57コマ目)
  37. 6.2 250k-gate FPGA Implementation/p103 (59コマ目)
  38. 6.3 Summary/p111 (63コマ目)
  39. 7 Conclusion/p113 (64コマ目)
14access

Codes

  • NII Article ID (NAID)
    500000188398
  • NII Author ID (NRID)
    • 8000000188681
  • DOI(NDL)
  • Text Lang
    • eng
  • NDLBibID
    • 000000352712
  • Source
    • Institutional Repository
    • NDL ONLINE
    • NDL Digital Collections
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